//displayx86.rs
use arch::x86::archx86::*;
use arch::x86::prefixx86::*;
use arch::x86::opcodex86::*;
use arch::x86::disasmtablesx86::*;
use arch::x86::registersx86::*;
use arch::x86::instructionsx86::*;
use disasm::*;
use std::fmt::Debug;

pub const DISASMX86_REG_MAP: [&'static str; 234] = [
    "",
    "ah",
    "al",
    "ax",
    "bh",
    "bl",
    "bp",
    "bpl",
    "bx",
    "ch",
    "cl",
    "cs",
    "cx",
    "dh",
    "di",
    "dil",
    "dl",
    "ds",
    "dx",
    "eax",
    "ebp",
    "ebx",
    "ecx",
    "edi",
    "edx",
    "flags",
    "eip",
    "eiz",
    "es",
    "esi",
    "esp",
    "fpsw",
    "fs",
    "gs",
    "ip",
    "rax",
    "rbp",
    "rbx",
    "rcx",
    "rdi",
    "rdx",
    "rip",
    "riz",
    "rsi",
    "rsp",
    "si",
    "sil",
    "sp",
    "spl",
    "ss",
    "cr0",
    "cr1",
    "cr2",
    "cr3",
    "cr4",
    "cr5",
    "cr6",
    "cr7",
    "cr8",
    "cr9",
    "cr10",
    "cr11",
    "cr12",
    "cr13",
    "cr14",
    "cr15",
    "dr0",
    "dr1",
    "dr2",
    "dr3",
    "dr4",
    "dr5",
    "dr6",
    "dr7",
    "fp0",
    "fp1",
    "fp2",
    "fp3",
    "fp4",
    "fp5",
    "fp6",
    "fp7",
    "k0",
    "k1",
    "k2",
    "k3",
    "k4",
    "k5",
    "k6",
    "k7",
    "mm0",
    "mm1",
    "mm2",
    "mm3",
    "mm4",
    "mm5",
    "mm6",
    "mm7",
    "r8",
    "r9",
    "r10",
    "r11",
    "r12",
    "r13",
    "r14",
    "r15",
    "st(0",
    "st(1)",
    "st(2)",
    "st(3)",
    "st(4)",
    "st(5)",
    "st(6)",
    "st(7)",
    "xmm0",
    "xmm1",
    "xmm2",
    "xmm3",
    "xmm4",
    "xmm5",
    "xmm6",
    "xmm7",
    "xmm8",
    "xmm9",
    "xmm10",
    "xmm11",
    "xmm12",
    "xmm13",
    "xmm14",
    "xmm15",
    "xmm16",
    "xmm17",
    "xmm18",
    "xmm19",
    "xmm20",
    "xmm21",
    "xmm22",
    "xmm23",
    "xmm24",
    "xmm25",
    "xmm26",
    "xmm27",
    "xmm28",
    "xmm29",
    "xmm30",
    "xmm31",
    "ymm0",
    "ymm1",
    "ymm2",
    "ymm3",
    "ymm4",
    "ymm5",
    "ymm6",
    "ymm7",
    "ymm8",
    "ymm9",
    "ymm10",
    "ymm11",
    "ymm12",
    "ymm13",
    "ymm14",
    "ymm15",
    "ymm16",
    "ymm17",
    "ymm18",
    "ymm19",
    "ymm20",
    "ymm21",
    "ymm22",
    "ymm23",
    "ymm24",
    "ymm25",
    "ymm26",
    "ymm27",
    "ymm28",
    "ymm29",
    "ymm30",
    "ymm31",
    "zmm0",
    "zmm1",
    "zmm2",
    "zmm3",
    "zmm4",
    "zmm5",
    "zmm6",
    "zmm7",
    "zmm8",
    "zmm9",
    "zmm10",
    "zmm11",
    "zmm12",
    "zmm13",
    "zmm14",
    "zmm15",
    "zmm16",
    "zmm17",
    "zmm18",
    "zmm19",
    "zmm20",
    "zmm21",
    "zmm22",
    "zmm23",
    "zmm24",
    "zmm25",
    "zmm26",
    "zmm27",
    "zmm28",
    "zmm29",
    "zmm30",
    "zmm31",
    "r8b",
    "r9b",
    "r10b",
    "r11b",
    "r12b",
    "r13b",
    "r14b",
    "r15b",
    "r8d",
    "r9d",
    "r10d",
    "r11d",
    "r12d",
    "r13d",
    "r14d",
    "r15d",
    "r8w",
    "r9w",
    "r10w",
    "r11w",
    "r12w",
    "r13w",
    "r14w",
    "r15w",
];

pub const DISASMX86_OP_MAP: [&'static str; 1296] = [
    "",
    "aaa",
    "aad",
    "aam",
    "aas",
    "fabs",
    "adc",
    "adcx",
    "add",
    "addpd",
    "addps",
    "addsd",
    "addss",
    "addsubpd",
    "addsubps",
    "fadd",
    "fiadd",
    "faddp",
    "adox",
    "aesdeclast",
    "aesdec",
    "aesenclast",
    "aesenc",
    "aesimc",
    "aeskeygenassist",
    "and",
    "andn",
    "andnpd",
    "andnps",
    "andpd",
    "andps",
    "arpl",
    "bextr",
    "blcfill",
    "blci",
    "blcic",
    "blcmsk",
    "blcs",
    "blendpd",
    "blendps",
    "blendvpd",
    "blendvps",
    "blsfill",
    "blsi",
    "blsic",
    "blsmsk",
    "blsr",
    "bound",
    "bsf",
    "bsr",
    "bswap",
    "bt",
    "btc",
    "btr",
    "bts",
    "bzhi",
    "call",
    "cbw",
    "cdq",
    "cdqe",
    "fchs",
    "clac",
    "clc",
    "cld",
    "clflush",
    "clgi",
    "cli",
    "clts",
    "cmc",
    "cmova",
    "cmovae",
    "cmovb",
    "cmovbe",
    "fcmovbe",
    "fcmovb",
    "cmove",
    "fcmove",
    "cmovg",
    "cmovge",
    "cmovl",
    "cmovle",
    "fcmovnbe",
    "fcmovnb",
    "cmovne",
    "fcmovne",
    "cmovno",
    "cmovnp",
    "fcmovnu",
    "cmovns",
    "cmovo",
    "cmovp",
    "fcmovu",
    "cmovs",
    "cmp",
    "cmppd",
    "cmpps",
    "cmpsb",
    "cmpsd",
    "cmpsq",
    "cmpss",
    "cmpsw",
    "cmpxchg16b",
    "cmpxchg",
    "cmpxchg8b",
    "comisd",
    "comiss",
    "fcomp",
    "fcompi",
    "fcomi",
    "fcom",
    "fcos",
    "cpuid",
    "cqo",
    "crc32",
    "cvtdq2pd",
    "cvtdq2ps",
    "cvtpd2dq",
    "cvtpd2ps",
    "cvtps2dq",
    "cvtps2pd",
    "cvtsd2si",
    "cvtsd2ss",
    "cvtsi2sd",
    "cvtsi2ss",
    "cvtss2sd",
    "cvtss2si",
    "cvttpd2dq",
    "cvttps2dq",
    "cvttsd2si",
    "cvttss2si",
    "cwd",
    "cwde",
    "daa",
    "das",
    "data16",
    "dec",
    "div",
    "divpd",
    "divps",
    "fdivr",
    "fidivr",
    "fdivrp",
    "divsd",
    "divss",
    "fdiv",
    "fidiv",
    "fdivp",
    "dppd",
    "dpps",
    "ret",
    "encls",
    "enclu",
    "enter",
    "extractps",
    "extrq",
    "f2xm1",
    "lcall",
    "ljmp",
    "fbld",
    "fbstp",
    "fcompp",
    "fdecstp",
    "femms",
    "ffree",
    "ficom",
    "ficomp",
    "fincstp",
    "fldcw",
    "fldenv",
    "fldl2e",
    "fldl2t",
    "fldlg2",
    "fldln2",
    "fldpi",
    "fnclex",
    "fninit",
    "fnop",
    "fnstcw",
    "fnstsw",
    "fpatan",
    "fprem",
    "fprem1",
    "fptan",
    "frndint",
    "frstor",
    "fnsave",
    "fscale",
    "fsetpm",
    "fsincos",
    "fnstenv",
    "fxam",
    "fxrstor",
    "fxrstor64",
    "fxsave",
    "fxsave64",
    "fxtract",
    "fyl2x",
    "fyl2xp1",
    "movapd",
    "movaps",
    "orpd",
    "orps",
    "vmovapd",
    "vmovaps",
    "xorpd",
    "xorps",
    "getsec",
    "haddpd",
    "haddps",
    "hlt",
    "hsubpd",
    "hsubps",
    "idiv",
    "fild",
    "imul",
    "in",
    "inc",
    "insb",
    "insertps",
    "insertq",
    "insd",
    "insw",
    "int",
    "int1",
    "int3",
    "into",
    "invd",
    "invept",
    "invlpg",
    "invlpga",
    "invpcid",
    "invvpid",
    "iret",
    "iretd",
    "iretq",
    "fisttp",
    "fist",
    "fistp",
    "ucomisd",
    "ucomiss",
    "vcmp",
    "vcomisd",
    "vcomiss",
    "vcvtsd2ss",
    "vcvtsi2sd",
    "vcvtsi2ss",
    "vcvtss2sd",
    "vcvttsd2si",
    "vcvttsd2usi",
    "vcvttss2si",
    "vcvttss2usi",
    "vcvtusi2sd",
    "vcvtusi2ss",
    "vucomisd",
    "vucomiss",
    "jae",
    "ja",
    "jbe",
    "jb",
    "jcxz",
    "jecxz",
    "je",
    "jge",
    "jg",
    "jle",
    "jl",
    "jmp",
    "jne",
    "jno",
    "jnp",
    "jns",
    "jo",
    "jp",
    "jrcxz",
    "js",
    "kandb",
    "kandd",
    "kandnb",
    "kandnd",
    "kandnq",
    "kandnw",
    "kandq",
    "kandw",
    "kmovb",
    "kmovd",
    "kmovq",
    "kmovw",
    "knotb",
    "knotd",
    "knotq",
    "knotw",
    "korb",
    "kord",
    "korq",
    "kortestw",
    "korw",
    "kshiftlw",
    "kshiftrw",
    "kunpckbw",
    "kxnorb",
    "kxnord",
    "kxnorq",
    "kxnorw",
    "kxorb",
    "kxord",
    "kxorq",
    "kxorw",
    "lahf",
    "lar",
    "lddqu",
    "ldmxcsr",
    "lds",
    "fldz",
    "fld1",
    "fld",
    "lea",
    "leave",
    "les",
    "lfence",
    "lfs",
    "lgdt",
    "lgs",
    "lidt",
    "lldt",
    "lmsw",
    "or",
    "sub",
    "xor",
    "lodsb",
    "lodsd",
    "lodsq",
    "lodsw",
    "loop",
    "loope",
    "loopne",
    "retf",
    "retfq",
    "lsl",
    "lss",
    "ltr",
    "xadd",
    "lzcnt",
    "maskmovdqu",
    "maxpd",
    "maxps",
    "maxsd",
    "maxss",
    "mfence",
    "minpd",
    "minps",
    "minsd",
    "minss",
    "cvtpd2pi",
    "cvtpi2pd",
    "cvtpi2ps",
    "cvtps2pi",
    "cvttpd2pi",
    "cvttps2pi",
    "emms",
    "maskmovq",
    "movd",
    "movdq2q",
    "movntq",
    "movq2dq",
    "movq",
    "pabsb",
    "pabsd",
    "pabsw",
    "packssdw",
    "packsswb",
    "packuswb",
    "paddb",
    "paddd",
    "paddq",
    "paddsb",
    "paddsw",
    "paddusb",
    "paddusw",
    "paddw",
    "palignr",
    "pandn",
    "pand",
    "pavgb",
    "pavgw",
    "pcmpeqb",
    "pcmpeqd",
    "pcmpeqw",
    "pcmpgtb",
    "pcmpgtd",
    "pcmpgtw",
    "pextrw",
    "phaddsw",
    "phaddw",
    "phaddd",
    "phsubd",
    "phsubsw",
    "phsubw",
    "pinsrw",
    "pmaddubsw",
    "pmaddwd",
    "pmaxsw",
    "pmaxub",
    "pminsw",
    "pminub",
    "pmovmskb",
    "pmulhrsw",
    "pmulhuw",
    "pmulhw",
    "pmullw",
    "pmuludq",
    "por",
    "psadbw",
    "pshufb",
    "pshufw",
    "psignb",
    "psignd",
    "psignw",
    "pslld",
    "psllq",
    "psllw",
    "psrad",
    "psraw",
    "psrld",
    "psrlq",
    "psrlw",
    "psubb",
    "psubd",
    "psubq",
    "psubsb",
    "psubsw",
    "psubusb",
    "psubusw",
    "psubw",
    "punpckhbw",
    "punpckhdq",
    "punpckhwd",
    "punpcklbw",
    "punpckldq",
    "punpcklwd",
    "pxor",
    "monitor",
    "montmul",
    "mov",
    "movabs",
    "movbe",
    "movddup",
    "movdqa",
    "movdqu",
    "movhlps",
    "movhpd",
    "movhps",
    "movlhps",
    "movlpd",
    "movlps",
    "movmskpd",
    "movmskps",
    "movntdqa",
    "movntdq",
    "movnti",
    "movntpd",
    "movntps",
    "movntsd",
    "movntss",
    "movsb",
    "movsd",
    "movshdup",
    "movsldup",
    "movsq",
    "movss",
    "movsw",
    "movsx",
    "movsxd",
    "movupd",
    "movups",
    "movzx",
    "mpsadbw",
    "mul",
    "mulpd",
    "mulps",
    "mulsd",
    "mulss",
    "mulx",
    "fmul",
    "fimul",
    "fmulp",
    "mwait",
    "neg",
    "nop",
    "not",
    "out",
    "outsb",
    "outsd",
    "outsw",
    "packusdw",
    "pause",
    "pavgusb",
    "pblendvb",
    "pblendw",
    "pclmulqdq",
    "pcmpeqq",
    "pcmpestri",
    "pcmpestrm",
    "pcmpgtq",
    "pcmpistri",
    "pcmpistrm",
    "pdep",
    "pext",
    "pextrb",
    "pextrd",
    "pextrq",
    "pf2id",
    "pf2iw",
    "pfacc",
    "pfadd",
    "pfcmpeq",
    "pfcmpge",
    "pfcmpgt",
    "pfmax",
    "pfmin",
    "pfmul",
    "pfnacc",
    "pfpnacc",
    "pfrcpit1",
    "pfrcpit2",
    "pfrcp",
    "pfrsqit1",
    "pfrsqrt",
    "pfsubr",
    "pfsub",
    "phminposuw",
    "pi2fd",
    "pi2fw",
    "pinsrb",
    "pinsrd",
    "pinsrq",
    "pmaxsb",
    "pmaxsd",
    "pmaxud",
    "pmaxuw",
    "pminsb",
    "pminsd",
    "pminud",
    "pminuw",
    "pmovsxbd",
    "pmovsxbq",
    "pmovsxbw",
    "pmovsxdq",
    "pmovsxwd",
    "pmovsxwq",
    "pmovzxbd",
    "pmovzxbq",
    "pmovzxbw",
    "pmovzxdq",
    "pmovzxwd",
    "pmovzxwq",
    "pmuldq",
    "pmulhrw",
    "pmulld",
    "pop",
    "popaw",
    "popal",
    "popcnt",
    "popf",
    "popfd",
    "popfq",
    "prefetch",
    "prefetchnta",
    "prefetcht0",
    "prefetcht1",
    "prefetcht2",
    "prefetchw",
    "pshufd",
    "pshufhw",
    "pshuflw",
    "pslldq",
    "psrldq",
    "pswapd",
    "ptest",
    "punpckhqdq",
    "punpcklqdq",
    "push",
    "pushaw",
    "pushal",
    "pushf",
    "pushfd",
    "pushfq",
    "rcl",
    "rcpps",
    "rcpss",
    "rcr",
    "rdfsbase",
    "rdgsbase",
    "rdmsr",
    "rdpmc",
    "rdrand",
    "rdseed",
    "rdtsc",
    "rdtscp",
    "rol",
    "ror",
    "rorx",
    "roundpd",
    "roundps",
    "roundsd",
    "roundss",
    "rsm",
    "rsqrtps",
    "rsqrtss",
    "sahf",
    "sal",
    "salc",
    "sar",
    "sarx",
    "sbb",
    "scasb",
    "scasd",
    "scasq",
    "scasw",
    "setae",
    "seta",
    "setbe",
    "setc",
    "setb",
    "sete",
    "setge",
    "setg",
    "setle",
    "setl",
    "setne",
    "setno",
    "setnp",
    "setns",
    "seto",
    "setp",
    "sets",
    "sfence",
    "sgdt",
    "sha1msg1",
    "sha1msg2",
    "sha1nexte",
    "sha1rnds4",
    "sha256msg1",
    "sha256msg2",
    "sha256rnds2",
    "shl",
    "shld",
    "shlx",
    "shr",
    "shrd",
    "shrx",
    "shufpd",
    "shufps",
    "sidt",
    "fsin",
    "skinit",
    "sldt",
    "smsw",
    "sqrtpd",
    "sqrtps",
    "sqrtsd",
    "sqrtss",
    "fsqrt",
    "stac",
    "stc",
    "std",
    "stgi",
    "sti",
    "stmxcsr",
    "stosb",
    "stosd",
    "stosq",
    "stosw",
    "str",
    "fst",
    "fstp",
    "fstpnce",
    "subpd",
    "subps",
    "fsubr",
    "fisubr",
    "fsubrp",
    "subsd",
    "subss",
    "fsub",
    "fisub",
    "fsubp",
    "swapgs",
    "syscall",
    "sysenter",
    "sysexit",
    "sysret",
    "t1mskc",
    "test",
    "ud2",
    "ftst",
    "tzcnt",
    "tzmsk",
    "fucompi",
    "fucomi",
    "fucompp",
    "fucomp",
    "fucom",
    "ud2b",
    "unpckhpd",
    "unpckhps",
    "unpcklpd",
    "unpcklps",
    "vaddpd",
    "vaddps",
    "vaddsd",
    "vaddss",
    "vaddsubpd",
    "vaddsubps",
    "vaesdeclast",
    "vaesdec",
    "vaesenclast",
    "vaesenc",
    "vaesimc",
    "vaeskeygenassist",
    "valignd",
    "valignq",
    "vandnpd",
    "vandnps",
    "vandpd",
    "vandps",
    "vblendmpd",
    "vblendmps",
    "vblendpd",
    "vblendps",
    "vblendvpd",
    "vblendvps",
    "vbroadcastf128",
    "vbroadcasti128",
    "vbroadcasti32x4",
    "vbroadcasti64x4",
    "vbroadcastsd",
    "vbroadcastss",
    "vcmppd",
    "vcmpps",
    "vcmpsd",
    "vcmpss",
    "vcvtdq2pd",
    "vcvtdq2ps",
    "vcvtpd2dqx",
    "vcvtpd2dq",
    "vcvtpd2psx",
    "vcvtpd2ps",
    "vcvtpd2udq",
    "vcvtph2ps",
    "vcvtps2dq",
    "vcvtps2pd",
    "vcvtps2ph",
    "vcvtps2udq",
    "vcvtsd2si",
    "vcvtsd2usi",
    "vcvtss2si",
    "vcvtss2usi",
    "vcvttpd2dqx",
    "vcvttpd2dq",
    "vcvttpd2udq",
    "vcvttps2dq",
    "vcvttps2udq",
    "vcvtudq2pd",
    "vcvtudq2ps",
    "vdivpd",
    "vdivps",
    "vdivsd",
    "vdivss",
    "vdppd",
    "vdpps",
    "verr",
    "verw",
    "vextractf128",
    "vextractf32x4",
    "vextractf64x4",
    "vextracti128",
    "vextracti32x4",
    "vextracti64x4",
    "vextractps",
    "vfmadd132pd",
    "vfmadd132ps",
    "vfmadd213pd",
    "vfmadd213ps",
    "vfmaddpd",
    "vfmadd231pd",
    "vfmaddps",
    "vfmadd231ps",
    "vfmaddsd",
    "vfmadd213sd",
    "vfmadd132sd",
    "vfmadd231sd",
    "vfmaddss",
    "vfmadd213ss",
    "vfmadd132ss",
    "vfmadd231ss",
    "vfmaddsub132pd",
    "vfmaddsub132ps",
    "vfmaddsub213pd",
    "vfmaddsub213ps",
    "vfmaddsubpd",
    "vfmaddsub231pd",
    "vfmaddsubps",
    "vfmaddsub231ps",
    "vfmsub132pd",
    "vfmsub132ps",
    "vfmsub213pd",
    "vfmsub213ps",
    "vfmsubadd132pd",
    "vfmsubadd132ps",
    "vfmsubadd213pd",
    "vfmsubadd213ps",
    "vfmsubaddpd",
    "vfmsubadd231pd",
    "vfmsubaddps",
    "vfmsubadd231ps",
    "vfmsubpd",
    "vfmsub231pd",
    "vfmsubps",
    "vfmsub231ps",
    "vfmsubsd",
    "vfmsub213sd",
    "vfmsub132sd",
    "vfmsub231sd",
    "vfmsubss",
    "vfmsub213ss",
    "vfmsub132ss",
    "vfmsub231ss",
    "vfnmadd132pd",
    "vfnmadd132ps",
    "vfnmadd213pd",
    "vfnmadd213ps",
    "vfnmaddpd",
    "vfnmadd231pd",
    "vfnmaddps",
    "vfnmadd231ps",
    "vfnmaddsd",
    "vfnmadd213sd",
    "vfnmadd132sd",
    "vfnmadd231sd",
    "vfnmaddss",
    "vfnmadd213ss",
    "vfnmadd132ss",
    "vfnmadd231ss",
    "vfnmsub132pd",
    "vfnmsub132ps",
    "vfnmsub213pd",
    "vfnmsub213ps",
    "vfnmsubpd",
    "vfnmsub231pd",
    "vfnmsubps",
    "vfnmsub231ps",
    "vfnmsubsd",
    "vfnmsub213sd",
    "vfnmsub132sd",
    "vfnmsub231sd",
    "vfnmsubss",
    "vfnmsub213ss",
    "vfnmsub132ss",
    "vfnmsub231ss",
    "vfrczpd",
    "vfrczps",
    "vfrczsd",
    "vfrczss",
    "vorpd",
    "vorps",
    "vxorpd",
    "vxorps",
    "vgatherdpd",
    "vgatherdps",
    "vgatherpf0dpd",
    "vgatherpf0dps",
    "vgatherpf0qpd",
    "vgatherpf0qps",
    "vgatherpf1dpd",
    "vgatherpf1dps",
    "vgatherpf1qpd",
    "vgatherpf1qps",
    "vgatherqpd",
    "vgatherqps",
    "vhaddpd",
    "vhaddps",
    "vhsubpd",
    "vhsubps",
    "vinsertf128",
    "vinsertf32x4",
    "vinsertf64x4",
    "vinserti128",
    "vinserti32x4",
    "vinserti64x4",
    "vinsertps",
    "vlddqu",
    "vldmxcsr",
    "vmaskmovdqu",
    "vmaskmovpd",
    "vmaskmovps",
    "vmaxpd",
    "vmaxps",
    "vmaxsd",
    "vmaxss",
    "vmcall",
    "vmclear",
    "vmfunc",
    "vminpd",
    "vminps",
    "vminsd",
    "vminss",
    "vmlaunch",
    "vmload",
    "vmmcall",
    "vmovq",
    "vmovddup",
    "vmovd",
    "vmovdqa32",
    "vmovdqa64",
    "vmovdqa",
    "vmovdqu16",
    "vmovdqu32",
    "vmovdqu64",
    "vmovdqu8",
    "vmovdqu",
    "vmovhlps",
    "vmovhpd",
    "vmovhps",
    "vmovlhps",
    "vmovlpd",
    "vmovlps",
    "vmovmskpd",
    "vmovmskps",
    "vmovntdqa",
    "vmovntdq",
    "vmovntpd",
    "vmovntps",
    "vmovsd",
    "vmovshdup",
    "vmovsldup",
    "vmovss",
    "vmovupd",
    "vmovups",
    "vmpsadbw",
    "vmptrld",
    "vmptrst",
    "vmread",
    "vmresume",
    "vmrun",
    "vmsave",
    "vmulpd",
    "vmulps",
    "vmulsd",
    "vmulss",
    "vmwrite",
    "vmxoff",
    "vmxon",
    "vpabsb",
    "vpabsd",
    "vpabsq",
    "vpabsw",
    "vpackssdw",
    "vpacksswb",
    "vpackusdw",
    "vpackuswb",
    "vpaddb",
    "vpaddd",
    "vpaddq",
    "vpaddsb",
    "vpaddsw",
    "vpaddusb",
    "vpaddusw",
    "vpaddw",
    "vpalignr",
    "vpandd",
    "vpandnd",
    "vpandnq",
    "vpandn",
    "vpandq",
    "vpand",
    "vpavgb",
    "vpavgw",
    "vpblendd",
    "vpblendmd",
    "vpblendmq",
    "vpblendvb",
    "vpblendw",
    "vpbroadcastb",
    "vpbroadcastd",
    "vpbroadcastmb2q",
    "vpbroadcastmw2d",
    "vpbroadcastq",
    "vpbroadcastw",
    "vpclmulqdq",
    "vpcmov",
    "vpcmp",
    "vpcmpd",
    "vpcmpeqb",
    "vpcmpeqd",
    "vpcmpeqq",
    "vpcmpeqw",
    "vpcmpestri",
    "vpcmpestrm",
    "vpcmpgtb",
    "vpcmpgtd",
    "vpcmpgtq",
    "vpcmpgtw",
    "vpcmpistri",
    "vpcmpistrm",
    "vpcmpq",
    "vpcmpud",
    "vpcmpuq",
    "vpcomb",
    "vpcomd",
    "vpcomq",
    "vpcomub",
    "vpcomud",
    "vpcomuq",
    "vpcomuw",
    "vpcomw",
    "vpconflictd",
    "vpconflictq",
    "vperm2f128",
    "vperm2i128",
    "vpermd",
    "vpermi2d",
    "vpermi2pd",
    "vpermi2ps",
    "vpermi2q",
    "vpermil2pd",
    "vpermil2ps",
    "vpermilpd",
    "vpermilps",
    "vpermpd",
    "vpermps",
    "vpermq",
    "vpermt2d",
    "vpermt2pd",
    "vpermt2ps",
    "vpermt2q",
    "vpextrb",
    "vpextrd",
    "vpextrq",
    "vpextrw",
    "vpgatherdd",
    "vpgatherdq",
    "vpgatherqd",
    "vpgatherqq",
    "vphaddbd",
    "vphaddbq",
    "vphaddbw",
    "vphadddq",
    "vphaddd",
    "vphaddsw",
    "vphaddubd",
    "vphaddubq",
    "vphaddubw",
    "vphaddudq",
    "vphadduwd",
    "vphadduwq",
    "vphaddwd",
    "vphaddwq",
    "vphaddw",
    "vphminposuw",
    "vphsubbw",
    "vphsubdq",
    "vphsubd",
    "vphsubsw",
    "vphsubwd",
    "vphsubw",
    "vpinsrb",
    "vpinsrd",
    "vpinsrq",
    "vpinsrw",
    "vplzcntd",
    "vplzcntq",
    "vpmacsdd",
    "vpmacsdqh",
    "vpmacsdql",
    "vpmacssdd",
    "vpmacssdqh",
    "vpmacssdql",
    "vpmacsswd",
    "vpmacssww",
    "vpmacswd",
    "vpmacsww",
    "vpmadcsswd",
    "vpmadcswd",
    "vpmaddubsw",
    "vpmaddwd",
    "vpmaskmovd",
    "vpmaskmovq",
    "vpmaxsb",
    "vpmaxsd",
    "vpmaxsq",
    "vpmaxsw",
    "vpmaxub",
    "vpmaxud",
    "vpmaxuq",
    "vpmaxuw",
    "vpminsb",
    "vpminsd",
    "vpminsq",
    "vpminsw",
    "vpminub",
    "vpminud",
    "vpminuq",
    "vpminuw",
    "vpmovdb",
    "vpmovdw",
    "vpmovmskb",
    "vpmovqb",
    "vpmovqd",
    "vpmovqw",
    "vpmovsdb",
    "vpmovsdw",
    "vpmovsqb",
    "vpmovsqd",
    "vpmovsqw",
    "vpmovsxbd",
    "vpmovsxbq",
    "vpmovsxbw",
    "vpmovsxdq",
    "vpmovsxwd",
    "vpmovsxwq",
    "vpmovusdb",
    "vpmovusdw",
    "vpmovusqb",
    "vpmovusqd",
    "vpmovusqw",
    "vpmovzxbd",
    "vpmovzxbq",
    "vpmovzxbw",
    "vpmovzxdq",
    "vpmovzxwd",
    "vpmovzxwq",
    "vpmuldq",
    "vpmulhrsw",
    "vpmulhuw",
    "vpmulhw",
    "vpmulld",
    "vpmullw",
    "vpmuludq",
    "vpord",
    "vporq",
    "vpor",
    "vpperm",
    "vprotb",
    "vprotd",
    "vprotq",
    "vprotw",
    "vpsadbw",
    "vpscatterdd",
    "vpscatterdq",
    "vpscatterqd",
    "vpscatterqq",
    "vpshab",
    "vpshad",
    "vpshaq",
    "vpshaw",
    "vpshlb",
    "vpshld",
    "vpshlq",
    "vpshlw",
    "vpshufb",
    "vpshufd",
    "vpshufhw",
    "vpshuflw",
    "vpsignb",
    "vpsignd",
    "vpsignw",
    "vpslldq",
    "vpslld",
    "vpsllq",
    "vpsllvd",
    "vpsllvq",
    "vpsllw",
    "vpsrad",
    "vpsraq",
    "vpsravd",
    "vpsravq",
    "vpsraw",
    "vpsrldq",
    "vpsrld",
    "vpsrlq",
    "vpsrlvd",
    "vpsrlvq",
    "vpsrlw",
    "vpsubb",
    "vpsubd",
    "vpsubq",
    "vpsubsb",
    "vpsubsw",
    "vpsubusb",
    "vpsubusw",
    "vpsubw",
    "vptestmd",
    "vptestmq",
    "vptestnmd",
    "vptestnmq",
    "vptest",
    "vpunpckhbw",
    "vpunpckhdq",
    "vpunpckhqdq",
    "vpunpckhwd",
    "vpunpcklbw",
    "vpunpckldq",
    "vpunpcklqdq",
    "vpunpcklwd",
    "vpxord",
    "vpxorq",
    "vpxor",
    "vrcp14pd",
    "vrcp14ps",
    "vrcp14sd",
    "vrcp14ss",
    "vrcp28pd",
    "vrcp28ps",
    "vrcp28sd",
    "vrcp28ss",
    "vrcpps",
    "vrcpss",
    "vrndscalepd",
    "vrndscaleps",
    "vrndscalesd",
    "vrndscaless",
    "vroundpd",
    "vroundps",
    "vroundsd",
    "vroundss",
    "vrsqrt14pd",
    "vrsqrt14ps",
    "vrsqrt14sd",
    "vrsqrt14ss",
    "vrsqrt28pd",
    "vrsqrt28ps",
    "vrsqrt28sd",
    "vrsqrt28ss",
    "vrsqrtps",
    "vrsqrtss",
    "vscatterdpd",
    "vscatterdps",
    "vscatterpf0dpd",
    "vscatterpf0dps",
    "vscatterpf0qpd",
    "vscatterpf0qps",
    "vscatterpf1dpd",
    "vscatterpf1dps",
    "vscatterpf1qpd",
    "vscatterpf1qps",
    "vscatterqpd",
    "vscatterqps",
    "vshufpd",
    "vshufps",
    "vsqrtpd",
    "vsqrtps",
    "vsqrtsd",
    "vsqrtss",
    "vstmxcsr",
    "vsubpd",
    "vsubps",
    "vsubsd",
    "vsubss",
    "vtestpd",
    "vtestps",
    "vunpckhpd",
    "vunpckhps",
    "vunpcklpd",
    "vunpcklps",
    "vzeroall",
    "vzeroupper",
    "wait",
    "wbinvd",
    "wrfsbase",
    "wrgsbase",
    "wrmsr",
    "xabort",
    "xacquire",
    "xbegin",
    "xchg",
    "fxch",
    "xcryptcbc",
    "xcryptcfb",
    "xcryptctr",
    "xcryptecb",
    "xcryptofb",
    "xend",
    "xgetbv",
    "xlatb",
    "xrelease",
    "xrstor",
    "xrstor64",
    "xsave",
    "xsave64",
    "xsaveopt",
    "xsaveopt64",
    "xsetbv",
    "xsha1",
    "xsha256",
    "xstore",
    "xtest",
];

pub const DISASMX86_GROUP_MAP: [&'static str; 47] = [
    "",
    "jump",
    "call",
    "ret",
    "int",
    "iret",
    "vm",
    "3dnow",
    "aes",
    "adx",
    "avx",
    "avx2",
    "avx512",
    "bmi",
    "bmi2",
    "cmov",
    "fc16",
    "fma",
    "fma4",
    "fsgsbase",
    "hle",
    "mmx",
    "mode32",
    "mode64",
    "rtm",
    "sha",
    "sse1",
    "sse2",
    "sse3",
    "sse41",
    "sse42",
    "sse4a",
    "ssse3",
    "pclmul",
    "xop",
    "cdi",
    "eri",
    "tbm",
    "16bitmode",
    "not64bitmode",
    "sgx",
    "dqi",
    "bwi",
    "pfi",
    "vlx",
    "smap",
    "novlx",
];

pub const DISASMX86_OPLOOKUP_MAP: [u16; 6268] = [
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    1,
    2,
    3,
    4,
    5,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    6,
    7,
    7,
    7,
    7,
    8,
    8,
    8,
    8,
    8,
    8,
    0,
    0,
    8,
    8,
    0,
    8,
    8,
    8,
    8,
    8,
    8,
    8,
    0,
    0,
    8,
    8,
    0,
    8,
    8,
    8,
    8,
    8,
    8,
    0,
    8,
    0,
    8,
    8,
    0,
    8,
    8,
    8,
    8,
    8,
    8,
    8,
    8,
    8,
    9,
    9,
    10,
    10,
    11,
    11,
    11,
    11,
    12,
    12,
    12,
    12,
    13,
    13,
    14,
    14,
    15,
    15,
    16,
    16,
    17,
    15,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    15,
    0,
    0,
    0,
    0,
    18,
    18,
    18,
    18,
    19,
    19,
    20,
    20,
    21,
    21,
    22,
    22,
    23,
    23,
    24,
    24,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    25,
    26,
    26,
    26,
    26,
    27,
    27,
    28,
    28,
    29,
    29,
    30,
    30,
    31,
    31,
    0,
    0,
    0,
    32,
    32,
    32,
    32,
    32,
    32,
    32,
    32,
    33,
    33,
    33,
    33,
    34,
    34,
    34,
    34,
    35,
    35,
    35,
    35,
    36,
    36,
    36,
    36,
    37,
    37,
    37,
    37,
    38,
    38,
    39,
    39,
    40,
    40,
    41,
    41,
    42,
    42,
    42,
    42,
    43,
    43,
    43,
    43,
    44,
    44,
    44,
    44,
    45,
    45,
    45,
    45,
    46,
    46,
    46,
    46,
    47,
    47,
    48,
    48,
    48,
    48,
    48,
    48,
    49,
    49,
    49,
    49,
    49,
    49,
    50,
    50,
    51,
    51,
    51,
    51,
    51,
    51,
    51,
    51,
    51,
    51,
    51,
    51,
    52,
    52,
    52,
    52,
    52,
    52,
    52,
    52,
    52,
    52,
    52,
    52,
    53,
    53,
    53,
    53,
    53,
    53,
    53,
    53,
    53,
    53,
    53,
    53,
    54,
    54,
    54,
    54,
    54,
    54,
    54,
    54,
    54,
    54,
    54,
    54,
    55,
    55,
    55,
    55,
    56,
    56,
    56,
    56,
    56,
    56,
    56,
    56,
    56,
    57,
    58,
    59,
    60,
    0,
    0,
    0,
    61,
    62,
    63,
    64,
    65,
    66,
    67,
    68,
    69,
    69,
    69,
    69,
    69,
    69,
    70,
    70,
    70,
    70,
    70,
    70,
    71,
    71,
    71,
    71,
    71,
    71,
    72,
    72,
    72,
    72,
    72,
    72,
    73,
    0,
    0,
    0,
    74,
    0,
    0,
    0,
    75,
    75,
    75,
    75,
    75,
    75,
    76,
    0,
    0,
    0,
    77,
    77,
    77,
    77,
    77,
    77,
    78,
    78,
    78,
    78,
    78,
    78,
    79,
    79,
    79,
    79,
    79,
    79,
    80,
    80,
    80,
    80,
    80,
    80,
    81,
    0,
    0,
    0,
    82,
    0,
    0,
    0,
    83,
    83,
    83,
    83,
    83,
    83,
    84,
    0,
    0,
    0,
    85,
    85,
    85,
    85,
    85,
    85,
    86,
    86,
    86,
    86,
    86,
    86,
    87,
    0,
    0,
    0,
    88,
    88,
    88,
    88,
    88,
    88,
    89,
    89,
    89,
    89,
    89,
    89,
    90,
    90,
    90,
    90,
    90,
    90,
    91,
    0,
    0,
    0,
    92,
    92,
    92,
    92,
    92,
    92,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    0,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    93,
    94,
    94,
    94,
    94,
    95,
    95,
    95,
    95,
    96,
    97,
    97,
    97,
    97,
    97,
    98,
    99,
    99,
    99,
    99,
    100,
    101,
    102,
    102,
    102,
    102,
    102,
    102,
    103,
    102,
    102,
    104,
    104,
    105,
    105,
    106,
    107,
    108,
    109,
    110,
    0,
    0,
    0,
    111,
    111,
    112,
    113,
    113,
    113,
    113,
    113,
    113,
    113,
    113,
    113,
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    0,
];

pub const DISASMX86_FIRST_OP_MAP: [u8; 6268] = [
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pub const REGSIZE32: [u8; 234] = [
    0,  
    1,  // ah
    1,  // al
    2,  // ax
    1,  // bh
    1,  // bl
    2,  // bp
    1,  // bpl
    2,  // bx
    1,  // ch
    1,  // cl
    2,  // cs
    2,  // cx
    1,  // dh
    2,  // di
    1,  // dil
    1,  // dl
    2,  // ds
    2,  // dx
    4,  // eax
    4,  // ebp
    4,  // ebx
    4,  // ecx
    4,  // edi
    4,  // edx
    4,  // flags
    4,  // eip
    4,  // eiz
    2,  // es
    4,  // esi
    4,  // esp
    10, // fpsw
    2,  // fs
    2,  // gs
    2,  // ip
    8,  // rax
    8,  // rbp
    8,  // rbx
    8,  // rcx
    8,  // rdi
    8,  // rdx
    8,  // rip
    8,  // riz
    8,  // rsi
    8,  // rsp
    2,  // si
    1,  // sil
    2,  // sp
    1,  // spl
    2,  // ss
    4,  // cr0
    4,  // cr1
    4,  // cr2
    4,  // cr3
    4,  // cr4
    8,  // cr5
    8,  // cr6
    8,  // cr7
    8,  // cr8
    8,  // cr9
    8,  // cr10
    8,  // cr11
    8,  // cr12
    8,  // cr13
    8,  // cr14
    8,  // cr15
    4,  // dr0
    4,  // dr1
    4,  // dr2
    4,  // dr3
    4,  // dr4
    4,  // dr5
    4,  // dr6
    4,  // dr7
    10, // fp0
    10, // fp1
    10, // fp2
    10, // fp3
    10, // fp4
    10, // fp5
    10, // fp6
    10, // fp7
    2,  // k0
    2,  // k1
    2,  // k2
    2,  // k3
    2,  // k4
    2,  // k5
    2,  // k6
    2,  // k7
    8,  // mm0
    8,  // mm1
    8,  // mm2
    8,  // mm3
    8,  // mm4
    8,  // mm5
    8,  // mm6
    8,  // mm7
    8,  // r8
    8,  // r9
    8,  // r10
    8,  // r11
    8,  // r12
    8,  // r13
    8,  // r14
    8,  // r15
    10, // st0
    10, // st1
    10, // st2
    10, // st3
    10, // st4
    10, // st5
    10, // st6
    10, // st7
    16, // xmm0
    16, // xmm1
    16, // xmm2
    16, // xmm3
    16, // xmm4
    16, // xmm5
    16, // xmm6
    16, // xmm7
    16, // xmm8
    16, // xmm9
    16, // xmm10
    16, // xmm11
    16, // xmm12
    16, // xmm13
    16, // xmm14
    16, // xmm15
    16, // xmm16
    16, // xmm17
    16, // xmm18
    16, // xmm19
    16, // xmm20
    16, // xmm21
    16, // xmm22
    16, // xmm23
    16, // xmm24
    16, // xmm25
    16, // xmm26
    16, // xmm27
    16, // xmm28
    16, // xmm29
    16, // xmm30
    16, // xmm31
    32, // ymm0
    32, // ymm1
    32, // ymm2
    32, // ymm3
    32, // ymm4
    32, // ymm5
    32, // ymm6
    32, // ymm7
    32, // ymm8
    32, // ymm9
    32, // ymm10
    32, // ymm11
    32, // ymm12
    32, // ymm13
    32, // ymm14
    32, // ymm15
    32, // ymm16
    32, // ymm17
    32, // ymm18
    32, // ymm19
    32, // ymm20
    32, // ymm21
    32, // ymm22
    32, // ymm23
    32, // ymm24
    32, // ymm25
    32, // ymm26
    32, // ymm27
    32, // ymm28
    32, // ymm29
    32, // ymm30
    32, // ymm31
    64, // zmm0
    64, // zmm1
    64, // zmm2
    64, // zmm3
    64, // zmm4
    64, // zmm5
    64, // zmm6
    64, // zmm7
    64, // zmm8
    64, // zmm9
    64, // zmm10
    64, // zmm11
    64, // zmm12
    64, // zmm13
    64, // zmm14
    64, // zmm15
    64, // zmm16
    64, // zmm17
    64, // zmm18
    64, // zmm19
    64, // zmm20
    64, // zmm21
    64, // zmm22
    64, // zmm23
    64, // zmm24
    64, // zmm25
    64, // zmm26
    64, // zmm27
    64, // zmm28
    64, // zmm29
    64, // zmm30
    64, // zmm31
    1,  // r8b
    1,  // r9b
    1,  // r10b
    1,  // r11b
    1,  // r12b
    1,  // r13b
    1,  // r14b
    1,  // r15b
    4,  // r8d
    4,  // r9d
    4,  // r10d
    4,  // r11d
    4,  // r12d
    4,  // r13d
    4,  // r14d
    4,  // r15d
    2,  // r8w
    2,  // r9w
    2,  // r10w
    2,  // r11w
    2,  // r12w
    2,  // r13w
    2,  // r14w
    2,  // r15w
];

pub const REGSIZE64: [u8; 234] = [
    0,  
    1,  // ah
    1,  // al
    2,  // ax
    1,  // bh
    1,  // bl
    2,  // bp
    1,  // bpl
    2,  // bx
    1,  // ch
    1,  // cl
    2,  // cs
    2,  // cx
    1,  // dh
    2,  // di
    1,  // dil
    1,  // dl
    2,  // ds
    2,  // dx
    4,  // eax
    4,  // ebp
    4,  // ebx
    4,  // ecx
    4,  // edi
    4,  // edx
    8,  // flags
    4,  // eip
    4,  // eiz
    2,  // es
    4,  // esi
    4,  // esp
    10, // fpsw
    2,  // fs
    2,  // gs
    2,  // ip
    8,  // rax
    8,  // rbp
    8,  // rbx
    8,  // rcx
    8,  // rdi
    8,  // rdx
    8,  // rip
    8,  // riz
    8,  // rsi
    8,  // rsp
    2,  // si
    1,  // sil
    2,  // sp
    1,  // spl
    2,  // ss
    8,  // cr0
    8,  // cr1
    8,  // cr2
    8,  // cr3
    8,  // cr4
    8,  // cr5
    8,  // cr6
    8,  // cr7
    8,  // cr8
    8,  // cr9
    8,  // cr10
    8,  // cr11
    8,  // cr12
    8,  // cr13
    8,  // cr14
    8,  // cr15
    8,  // dr0
    8,  // dr1
    8,  // dr2
    8,  // dr3
    8,  // dr4
    8,  // dr5
    8,  // dr6
    8,  // dr7
    10, // fp0
    10, // fp1
    10, // fp2
    10, // fp3
    10, // fp4
    10, // fp5
    10, // fp6
    10, // fp7
    2,  // k0
    2,  // k1
    2,  // k2
    2,  // k3
    2,  // k4
    2,  // k5
    2,  // k6
    2,  // k7
    8,  // mm0
    8,  // mm1
    8,  // mm2
    8,  // mm3
    8,  // mm4
    8,  // mm5
    8,  // mm6
    8,  // mm7
    8,  // r8
    8,  // r9
    8,  // r10
    8,  // r11
    8,  // r12
    8,  // r13
    8,  // r14
    8,  // r15
    10, // st0
    10, // st1
    10, // st2
    10, // st3
    10, // st4
    10, // st5
    10, // st6
    10, // st7
    16, // xmm0
    16, // xmm1
    16, // xmm2
    16, // xmm3
    16, // xmm4
    16, // xmm5
    16, // xmm6
    16, // xmm7
    16, // xmm8
    16, // xmm9
    16, // xmm10
    16, // xmm11
    16, // xmm12
    16, // xmm13
    16, // xmm14
    16, // xmm15
    16, // xmm16
    16, // xmm17
    16, // xmm18
    16, // xmm19
    16, // xmm20
    16, // xmm21
    16, // xmm22
    16, // xmm23
    16, // xmm24
    16, // xmm25
    16, // xmm26
    16, // xmm27
    16, // xmm28
    16, // xmm29
    16, // xmm30
    16, // xmm31
    32, // ymm0
    32, // ymm1
    32, // ymm2
    32, // ymm3
    32, // ymm4
    32, // ymm5
    32, // ymm6
    32, // ymm7
    32, // ymm8
    32, // ymm9
    32, // ymm10
    32, // ymm11
    32, // ymm12
    32, // ymm13
    32, // ymm14
    32, // ymm15
    32, // ymm16
    32, // ymm17
    32, // ymm18
    32, // ymm19
    32, // ymm20
    32, // ymm21
    32, // ymm22
    32, // ymm23
    32, // ymm24
    32, // ymm25
    32, // ymm26
    32, // ymm27
    32, // ymm28
    32, // ymm29
    32, // ymm30
    32, // ymm31
    64, // zmm0
    64, // zmm1
    64, // zmm2
    64, // zmm3
    64, // zmm4
    64, // zmm5
    64, // zmm6
    64, // zmm7
    64, // zmm8
    64, // zmm9
    64, // zmm10
    64, // zmm11
    64, // zmm12
    64, // zmm13
    64, // zmm14
    64, // zmm15
    64, // zmm16
    64, // zmm17
    64, // zmm18
    64, // zmm19
    64, // zmm20
    64, // zmm21
    64, // zmm22
    64, // zmm23
    64, // zmm24
    64, // zmm25
    64, // zmm26
    64, // zmm27
    64, // zmm28
    64, // zmm29
    64, // zmm30
    64, // zmm31
    1,  // r8b
    1,  // r9b
    1,  // r10b
    1,  // r11b
    1,  // r12b
    1,  // r13b
    1,  // r14b
    1,  // r15b
    4,  // r8d
    4,  // r9d
    4,  // r10d
    4,  // r11d
    4,  // r12d
    4,  // r13d
    4,  // r14d
    4,  // r15d
    2,  // r8w
    2,  // r9w
    2,  // r10w
    2,  // r11w
    2,  // r12w
    2,  // r13w
    2,  // r14w
    2,  // r15w
];

pub fn print_immediate_size(_size: u8)->String{
    match _size{
        1=>{return "byte ptr ".to_string()},
        2=>{return "word ptr ".to_string()},
        4=>{return "dword ptr ".to_string()},
        8=>{return "qword ptr ".to_string()},
        _=>{},
    }
    return String::new();
}
pub fn print_immediate(_imm: i64)->String{
    return String::new();
}
pub fn print_register(_reg: usize)->String{
    if _reg > 0 && (_reg as usize) < DISASMX86_REG_MAP.len(){
        return DISASMX86_REG_MAP[_reg as usize].to_string();
    }
    return String::new();
}

pub fn print_opcode(_index: usize)->&'static str{
    if _index > 0 && _index < DISASMX86_OPLOOKUP_MAP.len()
    {
        let op_index = DISASMX86_OPLOOKUP_MAP[_index] as usize;
        if op_index > 0 && op_index < DISASMX86_OP_MAP.len()
        {
            return DISASMX86_OP_MAP[op_index];
        }
    }
    return "";
}

pub enum SSECCx86 {
    INVALID = 0, // Uninitialized.
    EQ,
    LT,
    LE,
    UNORD,
    NEQ,
    NLT,
    NLE,
    ORD,
    EQUQ,
    NGE,
    NGT,
    FALSE,
    NEQOQ,
    GE,
    GT,
    TRUE,
}

pub enum AVXCCx86 {
    INVALID = 0, // Uninitialized.
    EQ,
    LT,
    LE,
    UNORD,
    NEQ,
    NLT,
    NLE,
    ORD,
    EQUQ,
    NGE,
    NGT,
    FALSE,
    NEQOQ,
    GE,
    GT,
    TRUE,
    EQOS,
    LTOQ,
    LEOQ,
    UNORDS,
    NEQUS,
    NLTUQ,
    NLEUQ,
    ORDS,
    EQUS,
    NGEUQ,
    NGTUQ,
    FALSEOS,
    NEQOS,
    GEOQ,
    GTOQ,
    TRUEUS,
}

pub enum AVXRMx86 {
    INVALID = 0, // Uninitialized.
    RN,  // Round to nearest
    RD,  // Round down
    RU,  // Round up
    RZ,  // Round toward zero
}

fn set_sse_cc<T: ArchDetail>(
    _detail: &mut T,
    _imm: i64)
{
    let sse_value = 
    match _imm & 7{
        0=>SSECCx86::EQ as u8,
        1=>SSECCx86::LT as u8,
        2=>SSECCx86::LE as u8,
        3=>SSECCx86::UNORD as u8,
        4=>SSECCx86::NEQ as u8,
        5=>SSECCx86::NLT as u8,
        6=>SSECCx86::NLE as u8,
        7=>SSECCx86::ORD as u8,
        8=>SSECCx86::EQUQ as u8,
        9=>SSECCx86::NGE as u8,
        0xa=>SSECCx86::NGT as u8,
        0xb=>SSECCx86::FALSE as u8,
        0xc=>SSECCx86::NEQOQ as u8,
        0xd=>SSECCx86::GE as u8,
        0xe=>SSECCx86::GT as u8,
        0xf=>SSECCx86::TRUE as u8,
        _=>0,
    };
    *_detail.sse_cc() = sse_value;
}

fn set_avx_cc<T: ArchDetail>(
    _detail: &mut T,
    _imm: i64)
{
    let avx_value = 
    match _imm & 0x1f{
        0=>AVXCCx86::EQ as u8,
        1=>AVXCCx86::LT as u8,
        2=>AVXCCx86::LE as u8,
        3=>AVXCCx86::UNORD as u8,
        4=>AVXCCx86::NEQ as u8,
        5=>AVXCCx86::NLT as u8,
        6=>AVXCCx86::NLE as u8,
        7=>AVXCCx86::ORD as u8,
        8=>AVXCCx86::EQUQ as u8,
        9=>AVXCCx86::NGE as u8,
        0xa=>AVXCCx86::NGT as u8,
        0xb=>AVXCCx86::FALSE as u8,
        0xc=>AVXCCx86::NEQOQ as u8,
        0xd=>AVXCCx86::GE as u8,
        0xe=>AVXCCx86::GT as u8,
        0xf=>AVXCCx86::TRUE as u8,
        0x10=>AVXCCx86::EQOS as u8,
        0x11=>AVXCCx86::LTOQ as u8,
        0x12=>AVXCCx86::LEOQ as u8,
        0x13=>AVXCCx86::UNORDS as u8,
        0x14=>AVXCCx86::NEQUS as u8,
        0x15=>AVXCCx86::NLTUQ as u8,
        0x16=>AVXCCx86::NLEUQ as u8,
        0x17=>AVXCCx86::ORDS as u8,
        0x18=>AVXCCx86::EQUS as u8,
        0x19=>AVXCCx86::NGEUQ as u8,
        0x1a=>AVXCCx86::NGTUQ as u8,
        0x1b=>AVXCCx86::FALSEOS as u8,
        0x1c=>AVXCCx86::NEQOS as u8,
        0x1d=>AVXCCx86::GEOQ as u8,
        0x1e=>AVXCCx86::GTOQ as u8,
        0x1f=>AVXCCx86::TRUEUS as u8,
        _=>0,
    };
    *_detail.avx_cc() = avx_value;
}

/// AVX_RM
fn set_rounding_cc<T: ArchDetail>(
    _detail: &mut T,
    _imm: u8)
{
    let avx_value = 
    match _imm & 0x3{
        0=>AVXRMx86::RN as u8,
        1=>AVXRMx86::RD as u8,
        2=>AVXRMx86::RU as u8,
        3=>AVXRMx86::RZ as u8,
         _=>0,
    };
    *_detail.avx_rm() = avx_value;
}
   
/// pc relative immediate
fn handle_pcrel_immediates(_instr: &Instructionx86, _immediate: &mut i64) -> bool{
    disasm_debug!("handle_pcrel_immediates()");
    let _opcode = _instr.instr_index as u32;
    let is_pcrel_opcode = match _opcode{
        o if o == Instructionsx86::CALL64pcrel32 as u32=>true,
        o if o == Instructionsx86::CALLpcrel16 as u32=>true,
        o if o == Instructionsx86::CALLpcrel32 as u32=>true,
        o if o == Instructionsx86::EHSjLjSetup as u32=>true,
        o if o == Instructionsx86::JAE1 as u32=>true,
        o if o == Instructionsx86::JAE2 as u32=>true,
        o if o == Instructionsx86::JAE4 as u32=>true,
        o if o == Instructionsx86::JA1 as u32=>true,
        o if o == Instructionsx86::JA2 as u32=>true,
        o if o == Instructionsx86::JA4 as u32=>true,
        o if o == Instructionsx86::JBE1 as u32=>true,
        o if o == Instructionsx86::JBE2 as u32=>true,
        o if o == Instructionsx86::JBE4 as u32=>true,
        o if o == Instructionsx86::JB1 as u32=>true,
        o if o == Instructionsx86::JB2 as u32=>true,
        o if o == Instructionsx86::JB4 as u32=>true,
        o if o == Instructionsx86::JCXZ as u32=>true,
        o if o == Instructionsx86::JECXZ32 as u32=>true,
        o if o == Instructionsx86::JECXZ64 as u32=>true,
        o if o == Instructionsx86::JE1 as u32=>true,
        o if o == Instructionsx86::JE2 as u32=>true,
        o if o == Instructionsx86::JE4 as u32=>true,
        o if o == Instructionsx86::JGE1 as u32=>true,
        o if o == Instructionsx86::JGE2 as u32=>true,
        o if o == Instructionsx86::JGE4 as u32=>true,
        o if o == Instructionsx86::JG1 as u32=>true,
        o if o == Instructionsx86::JG2 as u32=>true,
        o if o == Instructionsx86::JG4 as u32=>true,
        o if o == Instructionsx86::JLE1 as u32=>true,
        o if o == Instructionsx86::JLE2 as u32=>true,
        o if o == Instructionsx86::JLE4 as u32=>true,
        o if o == Instructionsx86::JL1 as u32=>true,
        o if o == Instructionsx86::JL2 as u32=>true,
        o if o == Instructionsx86::JL4 as u32=>true,
        o if o == Instructionsx86::JMP1 as u32=>true,
        o if o == Instructionsx86::JMP2 as u32=>true,
        o if o == Instructionsx86::JMP4 as u32=>true,
        o if o == Instructionsx86::JNE1 as u32=>true,
        o if o == Instructionsx86::JNE2 as u32=>true,
        o if o == Instructionsx86::JNE4 as u32=>true,
        o if o == Instructionsx86::JNO1 as u32=>true,
        o if o == Instructionsx86::JNO2 as u32=>true,
        o if o == Instructionsx86::JNO4 as u32=>true,
        o if o == Instructionsx86::JNP1 as u32=>true,
        o if o == Instructionsx86::JNP2 as u32=>true,
        o if o == Instructionsx86::JNP4 as u32=>true,
        o if o == Instructionsx86::JNS1 as u32=>true,
        o if o == Instructionsx86::JNS2 as u32=>true,
        o if o == Instructionsx86::JNS4 as u32=>true,
        o if o == Instructionsx86::JO1 as u32=>true,
        o if o == Instructionsx86::JO2 as u32=>true,
        o if o == Instructionsx86::JO4 as u32=>true,
        o if o == Instructionsx86::JP1 as u32=>true,
        o if o == Instructionsx86::JP2 as u32=>true,
        o if o == Instructionsx86::JP4 as u32=>true,
        o if o == Instructionsx86::JRCXZ as u32=>true,
        o if o == Instructionsx86::JS1 as u32=>true,
        o if o == Instructionsx86::JS2 as u32=>true,
        o if o == Instructionsx86::JS4 as u32=>true,
        o if o == Instructionsx86::LOOP as u32=>true,
        o if o == Instructionsx86::LOOPE as u32=>true,
        o if o == Instructionsx86::LOOPNE as u32=>true,
        o if o == Instructionsx86::TAILJMPd as u32=>true,
        o if o == Instructionsx86::TAILJMPd64 as u32=>true,
        o if o == Instructionsx86::W64ALLOCA as u32=>true,
        o if o == Instructionsx86::XBEGIN4 as u32=>true,
        _=>false,
    };
    // modify
    if is_pcrel_opcode{
        let mut imm: i64 = *_immediate as i64 +_instr.length as i64 + _instr.cinfo.offset as i64;
        if _instr.mode != Modex86::Mode64{
            imm = imm & 0xffffffff;
        }
        if _instr.mode == Modex86::Mode16 
        && _opcode != Instructionsx86::CALLpcrel32 as u32 
        && _opcode != Instructionsx86::JMP4 as u32 {
            imm = imm & 0xffff;
        }
        if _instr.mode == Modex86::Mode16 
        && _instr.prefix.kind[PrefixMaskx86::OPSize as usize] == 0
        && _opcode != Instructionsx86::JMP4 as u32{
            imm = imm & 0xffff;
        }
        if _opcode == Instructionsx86::CALLpcrel16 as u32 || _opcode == Instructionsx86::JMP2 as u32{
            imm = imm & 0xffff;
        }
        *_immediate = imm;
        return true;
    }
    return false;
}     

pub fn build_src_mem_operand<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _opcode: &u32,
    _segment_reg: u8,
    _base_reg: u8,
    _index_reg: u8,
    _offset_imm: i64,
    _scale_imm: i32,
    _size: u8,
    )
{
    disasm_debug!("build_mem_operand()");
    let mut mem_operand = String::new();
    if *_detail.op_count() >= 8 { return; }
    let index: usize = *_detail.op_count();
    _detail.operands()[index].op_type = InstrOpTypex86::Mem;
    _detail.operands()[index].size = _size;

     if _segment_reg != 0 {
        _detail.operands()[index].mem.segment=_segment_reg as i32;
        mem_operand = format!("{}:", print_register(_segment_reg as usize));
    }
    if _base_reg != 0 {
        _detail.operands()[index].mem.base=_base_reg as i32;
        mem_operand = format!("{}[{}", mem_operand, print_register(_base_reg as usize));
    }
    if _index_reg != 0 {
        _detail.operands()[index].mem.index=_index_reg as i32;
        mem_operand = format!("{}+{}", mem_operand, print_register(_index_reg as usize));
    }
    _detail.operands()[index].mem.displacement = _offset_imm;
    if _base_reg == 0 && _index_reg == 0 {
        match *_detail.address_size() {
            1=>{
                mem_operand = format!("{}[0x{:x}", mem_operand, _offset_imm as i8);
            },
            2=>{
                mem_operand = format!("{}[0x{:x}", mem_operand, _offset_imm as i16);
            },
            4=>{
                mem_operand = format!("{}[0x{:x}", mem_operand, _offset_imm as i32);
            },
            8=>{
                mem_operand = format!("{}[0x{:x}", mem_operand, _offset_imm as i64);
            },
            _=>{},
        } 
    } else if _offset_imm != 0 {
        let mut accumulator = "+";
        if _offset_imm < 0 {
            accumulator = "-";
        }
        match *_detail.address_size() {
            1=>{
                
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u8);
            },
            2=>{
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u16);
            },
            4=>{
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u32);
            },
            8=>{
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u64);
            },
            _=>{},
        } 
    }
    _detail.operands()[index].mem.scale = _scale_imm;
    if _scale_imm > 1 {
        mem_operand = format!("{}*0x{:x}", mem_operand, _scale_imm);
    }
    mem_operand = format!("{}]", mem_operand);
    *_detail.op_count()+=1;
    // print
    if index != 0 && DISASMX86_FIRST_OP_MAP[*_opcode as usize] == 0{
        // swap if no prior operand
        let temp = _detail.operands()[index];
        _detail.operands()[index] = _detail.operands()[0];
        _detail.operands()[0]=temp;
        *_nmemonic = format!("{}, {}", mem_operand, *_nmemonic);
        let last = _nmemonic.len()-2;
        _nmemonic.split_off(last);
    } else {
        *_nmemonic = format!("{}{}", *_nmemonic, mem_operand);
    }
}

pub fn build_mem_operand<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _segment_reg: u8,
    _base_reg: u8,
    _index_reg: u8,
    _offset_imm: i64,
    _scale_imm: i32,
    _size: u8,
    )
{
    disasm_debug!("build_mem_operand()");
    let mut mem_operand = String::new();
    if *_detail.op_count() >= 8 { return; }
    let index: usize = *_detail.op_count();
    _detail.operands()[index].op_type = InstrOpTypex86::Mem;
    _detail.operands()[index].size = _size;

    if _segment_reg != 0 {
        _detail.operands()[index].mem.segment=_segment_reg as i32;
        mem_operand = format!("{}:", print_register(_segment_reg as usize));
    }
    mem_operand = format!("{}[", mem_operand);
    if _base_reg != 0 {
        _detail.operands()[index].mem.base=_base_reg as i32;
        mem_operand = format!("{}{}", mem_operand, print_register(_base_reg as usize));
    }
    if _index_reg != 0 {

        _detail.operands()[index].mem.index=_index_reg as i32;
        if _base_reg == 0 {
            mem_operand = format!("{}{}", mem_operand, print_register(_index_reg as usize));
        } else {
            mem_operand = format!("{}+{}", mem_operand, print_register(_index_reg as usize));
        }   
    }
    _detail.operands()[index].mem.scale = _scale_imm;
    if _scale_imm != 0 && _index_reg !=0 {
        mem_operand = format!("{}*0x{:x}", mem_operand, _scale_imm);
    }
    _detail.operands()[index].mem.displacement = _offset_imm;
    if _base_reg == 0 && _index_reg == 0 {
        match *_detail.address_size() {
            1=>{
                mem_operand = format!("{}0x{:x}", mem_operand, _offset_imm as i8);
            },
            2=>{
                mem_operand = format!("{}0x{:x}", mem_operand, _offset_imm as i16);
            },
            4=>{
                mem_operand = format!("{}0x{:x}", mem_operand, _offset_imm as i32);
            },
            8=>{
                mem_operand = format!("{}0x{:x}", mem_operand, _offset_imm as i64);
            },
            _=>{},
        } 
    } else if _offset_imm != 0 {
        let mut accumulator = "+";
        if _offset_imm < 0 {
            accumulator = "-";
        }
        match *_detail.address_size() {
            1=>{
                
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u8);
            },
            2=>{
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u16);
            },
            4=>{
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u32);
            },
            8=>{
                mem_operand = format!("{}{}0x{:x}", mem_operand, accumulator, _offset_imm.abs() as u64);
            },
            _=>{},
        } 
    }
    
    mem_operand = format!("{}]", mem_operand);
    *_detail.op_count()+=1;
    // print
    *_nmemonic = format!("{}{}", *_nmemonic, mem_operand);
}

pub fn build_register<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _reg: u8,
    _size: u8)
{
    disasm_debug!("build_register() reg: {:?}", _reg);
    if *_detail.op_count() >= 8 ||  _reg == 0 { return; }
    let index: usize = *_detail.op_count();
    _detail.operands()[index].op_type = InstrOpTypex86::Reg;
    _detail.operands()[index].reg = _reg;
    let reg_size = match _detail.address_size(){
        8=>{REGSIZE64[_reg as usize]},
        _=>{REGSIZE32[_reg as usize]},
    };
    _detail.operands()[index].size = reg_size;
    *_detail.op_count()+=1;
    disasm_debug!("\treg: {:?}", _reg);
    // print
    *_nmemonic = format!("{}{}", *_nmemonic, print_register(_reg as usize));
}

pub fn build_immediate<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _imm: i64,
    _size: u8,
    _mode: &Modex86,
    _print: bool,
    _pc_relative: bool)
{
    disasm_debug!("build_immediate()");
    if *_detail.op_count() >= 8 { return; }
    let index: usize = *_detail.op_count();
    _detail.operands()[index].op_type = InstrOpTypex86::Imm;
    _detail.operands()[index].imm = _imm;
    _detail.operands()[index].size = _size;
    _detail.operands()[index].pc_relative_addr=_pc_relative;

    *_detail.op_count()+=1;
    if _print{
        match _size {
            1=>{
                *_nmemonic = format!("{}0x{:x}", *_nmemonic, _imm as i8);
            },
            2=>{
                *_nmemonic = format!("{}0x{:x}", *_nmemonic, _imm as i16);
            },
            4=>{
                *_nmemonic = format!("{}0x{:x}", *_nmemonic, _imm as i32);
            },
            8=>{
                *_nmemonic = format!("{}0x{:x}", *_nmemonic, _imm);
            },
            _=>{},
        } 
    }
}

pub fn build_immediates<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _imm: i64,
    _operand_pair: &OperandSetPair,
    _instr: &Instructionx86)->bool
{
    disasm_debug!("build_immediates()");
    let mut _immediate = _imm;
    let mut immedate_size: u8 = _instr.size.immediate;
    match _operand_pair.encodetype{
        OperandTypex86::TYPERELv=>{
            match _instr.size.displacement{
                1=>{
                    if (_immediate & 0x80) != 0{
                        _immediate |= !(0xff);
                    }
                },
                2=>{
                    if (_immediate & 0x8000) != 0{
                        _immediate |= !(0xffff);
                    }
                },
                4=>{
                    if (_immediate & 0x80000000) != 0{
                        _immediate |= !(0xffffffff);
                    }
                },
                8=>{ /* Do nothing */ },
                _=>{},
            }
        },
        OperandTypex86::TYPEIMM8 | 
        OperandTypex86::TYPEIMM16 |
        OperandTypex86::TYPEIMM32 |
        OperandTypex86::TYPEIMM64 |
        OperandTypex86::TYPEIMMv=>{
            let opcode = _instr.instr_index as u32;

            immedate_size = match _operand_pair.encodetype {
                OperandTypex86::TYPEIMM8=>1u8,
                OperandTypex86::TYPEIMM16=>2u8,
                OperandTypex86::TYPEIMM32=>4u8,
                OperandTypex86::TYPEIMM64=>8u8,
                _=>_instr.size.immediate,
            };
            
            match _operand_pair.encoding{
                OperandEncodingx86::ENCODINGIB=>{
                    let is_valid_opcode: bool = match opcode{
                        o if o == Instructionsx86::INT as u32=>false,
                        o if o == Instructionsx86::BLENDPSrri as u32=>false,
                        o if o == Instructionsx86::BLENDPDrri as u32=>false,
                        o if o == Instructionsx86::PBLENDWrri as u32=>false,
                        o if o == Instructionsx86::MPSADBWrri as u32=>false,
                        o if o == Instructionsx86::DPPSrri as u32=>false,
                        o if o == Instructionsx86::DPPDrri as u32=>false,
                        o if o == Instructionsx86::INSERTPSrr as u32=>false,
                        o if o == VInstructionsx86::VBLENDPSYrri as u32=>false,
                        o if o == VInstructionsx86::VBLENDPSYrmi as u32=>false,
                        o if o == VInstructionsx86::VBLENDPDYrri as u32=>false,
                        o if o == VInstructionsx86::VBLENDPDYrmi as u32=>false,
                        o if o == VInstructionsx86::VPBLENDWrri as u32=>false,
                        o if o == VInstructionsx86::VMPSADBWrri as u32=>false,
                        o if o == VInstructionsx86::VDPPSYrri as u32=>false,
                        o if o == VInstructionsx86::VDPPSYrmi as u32=>false,
                        o if o == VInstructionsx86::VDPPDrri as u32=>false,
                        o if o == VInstructionsx86::VINSERTPSrr as u32=>false,
                        _=>true,
                    };
                    if is_valid_opcode{
                        if (_immediate & 0x80) != 0{
                            _immediate |= !(0xff);
                        }
                    }
                },
                OperandEncodingx86::ENCODINGIW=>{
                    if (_immediate & 0x8000) != 0{
                        _immediate |= !(0xffff);
                    }
                },
                OperandEncodingx86::ENCODINGID=>{
                    if (_immediate & 0x80000000) != 0{
                        _immediate |= !(0xffffffff);
                    }
                },
                OperandEncodingx86::ENCODINGIO=>{
                    /* Do nothing */
                },
                _=>{},
            }
        },
        OperandTypex86::TYPEIMM3=>{
            let opcode = _instr.instr_index as u32;
            if _immediate <= 0xf {
                match opcode{
                    //CMPPD, CMPPS, CMPSD, CMPSS
                    550...553 | //CMPPD,
                    554...557 | //CMPPS,
                    559...562 | //CMPSD
                    565...568 // CMPSS
                    =>set_sse_cc(_detail, _immediate),
                    _=>{},
                }
            }
        },
        OperandTypex86::TYPEIMM5=>{
            let opcode = _instr.instr_index as u32;
            if _immediate <= 0x1f {
                if opcode == VInstructionsx86::VCMPPDrmi as u32||
                opcode == VInstructionsx86::VCMPPDrri as u32||
                opcode == VInstructionsx86::VCMPPSrmi as u32||
                opcode == VInstructionsx86::VCMPPSrri as u32||
                opcode == VInstructionsx86::VCMPSDrm as u32||
                opcode == VInstructionsx86::VCMPSDrr as u32||
                opcode == VInstructionsx86::VCMPSSrm as u32||
                opcode == VInstructionsx86::VCMPSSrr as u32||
                opcode == VInstructionsx86::VCMPPDYrmi as u32||
                opcode == VInstructionsx86::VCMPPDYrri as u32||
                opcode == VInstructionsx86::VCMPPSYrmi as u32||
                opcode == VInstructionsx86::VCMPPSYrri as u32||
                opcode == VInstructionsx86::VCMPPDZrmi as u32||
                opcode == VInstructionsx86::VCMPPDZrri as u32||
                opcode == VInstructionsx86::VCMPPSZrmi as u32||
                opcode == VInstructionsx86::VCMPPSZrri as u32||
                opcode == VInstructionsx86::VCMPSDZrm as u32||
                opcode == VInstructionsx86::VCMPSDZrr as u32||
                opcode == VInstructionsx86::VCMPSSZrm as u32||
                opcode == VInstructionsx86::VCMPSSZrr as u32
                { 
                    set_avx_cc(_detail, _immediate);
                }
                if opcode == VInstructionsx86::VCVTDQ2PSZrrb as u32 || 
                opcode == VInstructionsx86::VCVTPD2DQZrrb as u32 || 
                opcode == VInstructionsx86::VCVTPD2PSZrrb as u32 ||
                opcode == VInstructionsx86::VCVTPD2UDQZrrb as u32 ||
                opcode == VInstructionsx86::VCVTPS2DQZrrb as u32 ||
                opcode == VInstructionsx86::VCVTPS2UDQZrrb as u32 ||
                opcode == VInstructionsx86::VCVTUDQ2PSZrrb as u32
                {
                    set_rounding_cc(_detail, _immediate as u8);
                }
            }
        },
        OperandTypex86::TYPEXMM32=>{
            build_register(
                _detail, 
                _nmemonic, 
                Registersx86::XMM0 as u8 + (_immediate >> 4) as u8,
                4);
            return true;
        },
        OperandTypex86::TYPEXMM64=>{
            build_register(
                _detail, 
                _nmemonic, 
                Registersx86::XMM0 as u8 + (_immediate >> 4) as u8,
                8);
            return true;
        },
        OperandTypex86::TYPEXMM128=>{
            build_register(
                _detail, 
                _nmemonic, 
                Registersx86::XMM0 as u8 + (_immediate >> 4) as u8,
                16);
            return true;
        },
        OperandTypex86::TYPEXMM256=>{
            build_register(
                _detail, 
                _nmemonic,
                Registersx86::YMM0 as u8 + (_immediate >> 4) as u8,
                32);
            return true;
        },
        OperandTypex86::TYPEXMM512=>{
            build_register(
                _detail, 
                _nmemonic,
                Registersx86::ZMM0 as u8 + (_immediate >> 4) as u8,
                64);
            return true;
        },
        OperandTypex86::TYPEREL8=>{
            if (_immediate & 0x80) != 0 {
                _immediate |= !(0xff);
            }
        },
        OperandTypex86::TYPEREL32 | 
        OperandTypex86::TYPEREL64=>{
            if (_immediate & 0x80000000) != 0{
                _immediate |= !(0xffffffff);
            }
        },
        _=>{},
    }

    match _operand_pair.encodetype{
        OperandTypex86::TYPEMOFFS8 |
        OperandTypex86::TYPEMOFFS16 |
        OperandTypex86::TYPEMOFFS32 |
        OperandTypex86::TYPEMOFFS64=>{
            build_mem_operand(
                _detail,
                _nmemonic,
                _instr.prefix.segment,
                0,
                0,
                _immediate,
                0,
                _instr.operand_size as u8);
            //*_nmemonic= format!("{}, ", _nmemonic);
            return true;
        },
        _=>{},
    }
    let mut is_pcrel_opcode = false;
    
    if handle_pcrel_immediates(_instr, &mut _immediate){
        disasm_debug!("is_pcrel_opcode = true 0x{:x}", _immediate);
        immedate_size = _instr.size.address;
        is_pcrel_opcode = true;
    }

    disasm_debug!("imm size {}", immedate_size);
    // Set the immediate
    build_immediate(
        _detail,
        _nmemonic,
        _immediate as i64,
        immedate_size,
        &_instr.mode,
        true,
        is_pcrel_opcode);
    return true;
}

pub fn build_rm_register<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _operand_pair: &OperandSetPair,
    _instr: &Instructionx86)->bool
{
    disasm_debug!("build_rm_register()");
    match _instr.mod_rm{
        Some(ref rm)=>{
            disasm_debug!("rm.base_ea {}", rm.base_ea);
            if (rm.base_ea_reg < EABases::Max as u16) && (rm.base_ea == EABases::Sib as u16 || rm.base_ea == EABases::Sib64 as u16){
                disasm_debug!("\tA R/M register operand may not have a SIB byte");
                return false
            }
            match rm.base_ea{
                r if r == Registersx86::NoRegister as u16=>{ return false; },
                1...260=>{                    
                    match rm.kind {
                        RegType::AllRegisters=>{
                            let offset = rm.base_ea;
                            build_register(
                                _detail, 
                                _nmemonic,
                                AllRegisters::translate(offset as u8),
                                _instr.operand_size as u8);
                        },
                        RegType::EABases=>{
                            build_register(
                                _detail, 
                                _nmemonic,
                                EABases::translate(rm.base_ea as u8),
                                _instr.operand_size as u8);
                        },
                    }
                },
                _=>{
                    disasm_debug!("\tUnexpected EA base register");
                    return false
                },
            }
        },
        None=>{},
    }
    return true;
}

pub fn build_rm_memory<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _operand_pair: &OperandSetPair,
    _instr: &Instructionx86)->bool
{
    disasm_debug!("build_rm_memory()");
    let mut _segment_reg: u8 = 0;
    let mut _base_reg: u8 = 0;
    let mut _index_reg: u8 = 0;
    let mut _offset_imm: i64 = 0;
    let mut _scale_imm: i32 = 0;

    match _instr.mod_rm{
        Some(ref rm)=>{        
            if rm.base_ea == EABases::Sib as u16 || rm.base_ea == EABases::Sib64 as u16{
                match rm.sib{
                    Some(ref sib)=>{
                        if sib.sib_base != Registersx86::NoRegister as u8{
                            match sib.sib_base{
                                1...211=>{ // All Registers
                                    _base_reg = AllRegisters::translate(sib.sib_base);                                    
                                }
                                _=>{ 
                                    disasm_debug!("\tnot a valid register");
                                    return false;
                                }
                            }
                        } 
                        let opcode = _instr.instr_index as u32;
                        let is_index_128 = match opcode{
                            o if o == VInstructionsx86::VGATHERDPDrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERDPDYrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERQPDrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERDPSrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERQPSrm  as u32=>true,
                            o if o == VInstructionsx86::VPGATHERDQrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERDQYrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERQQrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERDDrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERQDrm as u32=>true,
                            _=>false,
                        };
                        let is_index_256 = match opcode{
                            o if o == VInstructionsx86::VGATHERQPDYrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERDPSYrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERQPSYrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERDPDZrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERDQZrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERQQYrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERDDYrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERQDYrm as u32=>true,
                            _=>false,
                        };
                        let is_index_512 = match opcode{
                            o if o == VInstructionsx86::VGATHERQPDZrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERDPSZrm as u32=>true,
                            o if o == VInstructionsx86::VGATHERQPSZrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERQQZrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERDDZrm as u32=>true,
                            o if o == VInstructionsx86::VPGATHERQDZrm as u32=>true,
                            _=>false,
                        };
                        let mut sib_index = sib.sib_index;

                        if is_index_128 || is_index_256 || is_index_512{
                            let index_reg = match _instr.size.address == 8 { true=>SibIndexes::RAX as u8, false=>SibIndexes::EAX as u8};
                            let index_offset = sib_index - index_reg;
                            let mut _index_base = 0;
                            if is_index_512 {
                                _index_base = SibIndexes::ZMM0 as u8;
                            } else if is_index_256 {
                                _index_base = SibIndexes::YMM0 as u8;
                            }
                            else {
                                _index_base = SibIndexes::XMM0 as u8;
                            }
                            
                            sib_index = _index_base + match sib_index{ 0=>4, _=>index_offset};
                        }
                        _index_reg = SibIndexes::translate(sib_index);
                        _scale_imm = sib.sib_scale as i32;
                    },
                    None=>{},
                }
            } else 
            {
                match rm.base_ea{
                    0=>{
                        if rm.displacement_ea == EADisplacement::Size0 {
                            disasm_debug!("\tdisplacement_ea is 0");
                            return false; 
                        }
                        if _instr.mode == Modex86::Mode64 {
                            if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                                _base_reg = Registersx86::EIP as u8;
                                
                            } else {
                               _base_reg = Registersx86::RIP as u8; 
                            }
                        }
                        _index_reg = 0;
                    },
                    b if b == EABases::BXSI as u16=>{
                        _base_reg = EABases::translate(rm.base_ea as u8);
                        _index_reg = Registersx86::SI as u8;
                    },
                    b if b == EABases::BXDI as u16=>{
                        _base_reg = EABases::translate(rm.base_ea as u8);
                        _index_reg = Registersx86::DI as u8;
                    },
                    b if b == EABases::BPSI as u16=>{
                        _base_reg = EABases::translate(rm.base_ea as u8);
                        _index_reg = Registersx86::SI as u8;
                    },
                    b if b == EABases::BPDI as u16=>{
                        _base_reg = EABases::translate(rm.base_ea as u8);
                        _index_reg = Registersx86::DI as u8;
                    },
                    _=>{
                        _index_reg = 0;
                        match _operand_pair.encoding{
                            OperandEncodingx86::ENCODINGRM |
                            OperandEncodingx86::ENCODINGRMCD2 |
                            OperandEncodingx86::ENCODINGRMCD4 |
                            OperandEncodingx86::ENCODINGRMCD8 |
                            OperandEncodingx86::ENCODINGRMCD16 |
                            OperandEncodingx86::ENCODINGRMCD32 |
                            OperandEncodingx86::ENCODINGRMCD64 =>{
                                _base_reg = EABases::translate(rm.base_ea as u8);
                            },
                            _=>{ 
                                disasm_debug!("\tnot a valid EABase");
                                return false; 
                            },
                        }
                    },
                }
                _scale_imm=1;
            }
            _segment_reg = _instr.prefix.segment;

            match rm.displacement{
                Some(ref disp)=>{  
                    _offset_imm = disp.data as i64;
                },
                None=>{},
            }

            let operand_size: u8 = match _operand_pair.encodetype{
                OperandTypex86::TYPEM8=>1,
                OperandTypex86::TYPEM16=>2,
                OperandTypex86::TYPEM32=>4,
                OperandTypex86::TYPEM64=>8,
                OperandTypex86::TYPEM128=>16,
                OperandTypex86::TYPEM256=>32,
                OperandTypex86::TYPEM512=>64,
                OperandTypex86::TYPEM32FP=>4,
                OperandTypex86::TYPEM64FP=>8,
                OperandTypex86::TYPEM80FP=>10,
                OperandTypex86::TYPEM16INT=>2,
                OperandTypex86::TYPEM32INT=>4,
                OperandTypex86::TYPEM64INT=>8,
                OperandTypex86::TYPEM1632=>6,
                OperandTypex86::TYPEM1664=>10,
                _=>_instr.operand_size as u8, //_instr.size.address as u8,
            };
            
            build_mem_operand(
                _detail,
                _nmemonic,
                _segment_reg,
                _base_reg,
                _index_reg,
                _offset_imm,
                _scale_imm,
                operand_size);
        },
        None=>{},
    }
    return true;
}

pub fn build_rm<T: ArchDetail>(
    _detail: &mut T,
    _nmemonic: &mut String,
    _operand_pair: &OperandSetPair,
    _instr: &Instructionx86)->bool
{
    disasm_debug!("build_rm()");
    match _operand_pair.encodetype{
        OperandTypex86::TYPER8 |
        OperandTypex86::TYPER16 |
        OperandTypex86::TYPER32 |
        OperandTypex86::TYPER64 |
        OperandTypex86::TYPERv |
        OperandTypex86::TYPEMM |
        OperandTypex86::TYPEMM32 |
        OperandTypex86::TYPEMM64 |
        OperandTypex86::TYPEXMM |
        OperandTypex86::TYPEXMM32 |
        OperandTypex86::TYPEXMM64 |
        OperandTypex86::TYPEXMM128 |
        OperandTypex86::TYPEXMM256 |
        OperandTypex86::TYPEXMM512 |
        OperandTypex86::TYPEVK1 |
        OperandTypex86::TYPEVK8 |
        OperandTypex86::TYPEVK16 |
        OperandTypex86::TYPEDEBUGREG |
        OperandTypex86::TYPECONTROLREG =>{
            if !build_rm_register(
                _detail, 
                _nmemonic,
                _operand_pair, 
                _instr)
            { 
                disasm_debug!("\tbuild_rm_register failed");
                return false; 
            }
        }
        OperandTypex86::TYPEM |
        OperandTypex86::TYPEM8 |
        OperandTypex86::TYPEM16 |
        OperandTypex86::TYPEM32 |
        OperandTypex86::TYPEM64 |
        OperandTypex86::TYPEM128 |
        OperandTypex86::TYPEM256 |
        OperandTypex86::TYPEM512 |
        OperandTypex86::TYPEMv |
        OperandTypex86::TYPEM32FP |
        OperandTypex86::TYPEM64FP |
        OperandTypex86::TYPEM80FP |
        OperandTypex86::TYPEM16INT |
        OperandTypex86::TYPEM32INT |
        OperandTypex86::TYPEM64INT |
        OperandTypex86::TYPEM1616 |
        OperandTypex86::TYPEM1632 |
        OperandTypex86::TYPEM1664 |
        OperandTypex86::TYPELEA=>{
            if !build_rm_memory(
                _detail, 
                _nmemonic,
                _operand_pair, 
                _instr)
            { 
                disasm_debug!("\tbuild_rm_memory failed");
                return false; 
            }
        }
        _=>{ return false; },
    }
    return true;
}

pub fn build_operand<T: ArchDetail + Debug>(
    _instr: &Instructionx86,
    _operand_pair: &OperandSetPair,
    _op_index: &mut usize,
    _instr_ext: &mut Instruction<T>,
    _immediates_translated: &mut usize,
    )->bool
{
    disasm_debug!("build_operand()");
    match _operand_pair.encoding{
        OperandEncodingx86::ENCODINGREG =>{
            match _instr.register{
                Some(ref reg)=>{
                    build_register(
                        &mut _instr_ext.detail, 
                        &mut _instr_ext.op_str,
                        AllRegisters::translate(reg.data),
                        _instr.operand_size as u8);
                    match _instr.operands
                    {
                        Some(ref operands)=>{
                            if operands[*_op_index+1].encoding != OperandEncodingx86::ENCODINGNONE{ 
                                _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
                            }
                        }
                        None=>{},
                    }
                },
                None=>{ return false },
            }
        },
        OperandEncodingx86::ENCODINGWRITEMASK =>{
            match _instr.register{
                Some(ref reg)=>{
                    if reg.mask >= 8 {
                        return false;
                    }
                    build_register(
                        &mut _instr_ext.detail, 
                        &mut _instr_ext.op_str,
                        AllRegisters::translate(AllRegisters::K0 as u8 + reg.mask),
                        _instr.operand_size as u8);
                },
                None=>{ return false },
            }
        },
        OperandEncodingx86::ENCODINGRM |
        OperandEncodingx86::ENCODINGRMCD2 |
        OperandEncodingx86::ENCODINGRMCD4 |
        OperandEncodingx86::ENCODINGRMCD8 |
        OperandEncodingx86::ENCODINGRMCD16 |
        OperandEncodingx86::ENCODINGRMCD32 |
        OperandEncodingx86::ENCODINGRMCD64 =>{
            if !build_rm(
                &mut _instr_ext.detail,
                &mut _instr_ext.op_str,
                _operand_pair,
                _instr)
            {
                disasm_debug!("\tbuild_rm failed");
                return false;
            }
            match _instr.operands
            {
                Some(ref operands)=>{
                    if operands[*_op_index+1].encoding != OperandEncodingx86::ENCODINGNONE{ 
                        _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
                    }
                },
                None=>{}
            }
        },
        OperandEncodingx86::ENCODINGCB |
        OperandEncodingx86::ENCODINGCW |
        OperandEncodingx86::ENCODINGCD |
        OperandEncodingx86::ENCODINGCP |
        OperandEncodingx86::ENCODINGCO |
        OperandEncodingx86::ENCODINGCT =>{
            return true;
        },
        OperandEncodingx86::ENCODINGIB |
        OperandEncodingx86::ENCODINGIW |
        OperandEncodingx86::ENCODINGID |
        OperandEncodingx86::ENCODINGIO |
        OperandEncodingx86::ENCODINGIv |
        OperandEncodingx86::ENCODINGIa =>{
            match _instr.immediates{
                Some(ref imm)=>{
                    if *_immediates_translated < imm.count as usize{
                        let immediate = imm.data[*_immediates_translated];
                        if !build_immediates(
                            &mut _instr_ext.detail,
                            &mut _instr_ext.op_str,
                            immediate, 
                            _operand_pair,
                            _instr)
                        {
                            disasm_debug!("\tbuild_immediates failed");
                            return false;
                        }
                        *_immediates_translated+=1;
                    }
                }
                None=>{ return false },
            }
        },
        OperandEncodingx86::ENCODINGSI =>{
            let base_reg: u8;
            if _instr.mode == Modex86::Mode64{
                if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                    base_reg = Registersx86::ESI as u8; 
                } else {
                    base_reg = Registersx86::RSI as u8; 
                }
            } else if _instr.mode == Modex86::Mode32{
                if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                    base_reg = Registersx86::SI as u8; 
                } else {
                    base_reg = Registersx86::ESI as u8; 
                }
            } else {
                if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                    base_reg = Registersx86::ESI as u8; 
                } else {
                    base_reg = Registersx86::SI as u8; 
                }
            }
            let operand_size: u8 = match _operand_pair.encodetype{
                OperandTypex86::TYPESRCIDX8=>1,
                OperandTypex86::TYPESRCIDX16=>2,
                OperandTypex86::TYPESRCIDX32=>4,
                OperandTypex86::TYPESRCIDX64=>8,
                _=>_instr.operand_size as u8,
            };
            disasm_debug!("\tENCODINGSI");
            build_src_mem_operand(
                &mut _instr_ext.detail,
                &mut _instr_ext.op_str,
                &_instr_ext.opcode,
                _instr.prefix.segment, // segment
                base_reg,
                0,
                0,
                0,
                operand_size);
        },
        OperandEncodingx86::ENCODINGDI =>{
            let base_reg: u8;
            if _instr.mode == Modex86::Mode64{
                if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                    base_reg = Registersx86::EDI as u8; 
                } else {
                    base_reg = Registersx86::RDI as u8; 
                }
            } else if _instr.mode == Modex86::Mode32{
                if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                    base_reg = Registersx86::DI as u8; 
                } else {
                    base_reg = Registersx86::EDI as u8; 
                }
            } else {
                if _instr.prefix.prefix_flags & PrefixMaskx86::ADDRSize as u32 != 0{
                    base_reg = Registersx86::EDI as u8; 
                } else {
                    base_reg = Registersx86::DI as u8; 
                }
            }
            disasm_debug!("\tENCODINGDI");
            let operand_size: u8 = match _operand_pair.encodetype{
                OperandTypex86::TYPEDSTIDX8=>1,
                OperandTypex86::TYPEDSTIDX16=>2,
                OperandTypex86::TYPEDSTIDX32=>4,
                OperandTypex86::TYPEDSTIDX64=>8,
                _=>_instr.operand_size as u8,
            };
            match _instr.mode{
                Modex86::Mode64=>{
                    build_mem_operand(
                        &mut _instr_ext.detail,
                        &mut _instr_ext.op_str,
                        0, // segment
                        base_reg,
                        0,
                        0,
                        0,
                        operand_size);
                },
                _=>{
                    build_mem_operand(
                        &mut _instr_ext.detail,
                        &mut _instr_ext.op_str,
                        Registersx86::ES as u8, // segment
                        base_reg,
                        0,
                        0,
                        0,
                        operand_size);
                },
            }
            match _instr.operands
            {
                Some(ref operands)=>{
                    if operands[*_op_index+1].encoding != OperandEncodingx86::ENCODINGNONE{ 
                        _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
                    }
                },
                None=>{}
            }
        },
        OperandEncodingx86::ENCODINGRB |
        OperandEncodingx86::ENCODINGRW |
        OperandEncodingx86::ENCODINGRD |
        OperandEncodingx86::ENCODINGRO |
        OperandEncodingx86::ENCODINGRv =>{
            match _instr.register{
                Some(ref reg)=>{
                    build_register(
                        &mut _instr_ext.detail, 
                        &mut _instr_ext.op_str,
                        AllRegisters::translate(reg.opcode_data),
                        _instr.operand_size as u8);
                    match _instr.operands
                    {
                        Some(ref operands)=>{
                            if operands[*_op_index+1].encoding != OperandEncodingx86::ENCODINGNONE{ 
                                _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
                            }
                        },
                        None=>{},
                    }
                    
                },
                None=>{ return false },
            }
        },
        OperandEncodingx86::ENCODINGFP =>{
            match _instr.mod_rm{
                Some(ref rm)=>{
                    let stack_pos =  Registersx86::ST0 as u16 + (rm.data & 7);
                    build_register(
                        &mut _instr_ext.detail, 
                        &mut _instr_ext.op_str,
                        stack_pos as u8,
                        _instr.operand_size as u8);
                }
                None=>{ return false },
            }
        },
        OperandEncodingx86::ENCODINGVVVV =>{
            match _instr.register{
                Some(ref reg)=>{
                    build_register(
                        &mut _instr_ext.detail, 
                        &mut _instr_ext.op_str,
                        AllRegisters::translate(reg.vvvv),
                        _instr.operand_size as u8);
                    match _instr.operands
                    {
                        Some(ref operands)=>{
                            if operands[*_op_index+1].encoding != OperandEncodingx86::ENCODINGNONE{ 
                                _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
                            }
                        },
                        None=>{},
                    }
                },
                None=>{ return false },
            }
        },
        OperandEncodingx86::ENCODINGDUP =>{
            disasm_debug!("\tDuplicate operand");
            match _instr.operands{
                Some(ref op)=>{
                    *_op_index+=1;
                    return build_operand(
                        _instr,
                        &op[*_op_index],
                        _op_index,
                        _instr_ext,
                        _immediates_translated);
                },
                None=>{ return false },
            }
        },
        _=>{},
    }
    return true;
}

fn check_bnd(_opcode: &u32) -> bool{
    match *_opcode {
        o if o == Instructionsx86::JAE1 as u32=>return true,
        o if o == Instructionsx86::JAE2 as u32=>return true,
        o if o == Instructionsx86::JAE4 as u32=>return true,
        o if o == Instructionsx86::JA1 as u32=>return true,
        o if o == Instructionsx86::JA2 as u32=>return true,
        o if o == Instructionsx86::JA4 as u32=>return true,
        o if o == Instructionsx86::JBE1 as u32=>return true,
        o if o == Instructionsx86::JBE2 as u32=>return true,
        o if o == Instructionsx86::JBE4 as u32=>return true,
        o if o == Instructionsx86::JB1 as u32=>return true,
        o if o == Instructionsx86::JB2 as u32=>return true,
        o if o == Instructionsx86::JB4 as u32=>return true,
        o if o == Instructionsx86::JCXZ as u32=>return true,
        o if o == Instructionsx86::JECXZ32 as u32=>return true,
        o if o == Instructionsx86::JECXZ64 as u32=>return true,
        o if o == Instructionsx86::JE1 as u32=>return true,
        o if o == Instructionsx86::JE2 as u32=>return true,
        o if o == Instructionsx86::JE4 as u32=>return true,
        o if o == Instructionsx86::JGE1 as u32=>return true,
        o if o == Instructionsx86::JGE2 as u32=>return true,
        o if o == Instructionsx86::JGE4 as u32=>return true,
        o if o == Instructionsx86::JG1 as u32=>return true,
        o if o == Instructionsx86::JG2 as u32=>return true,
        o if o == Instructionsx86::JG4 as u32=>return true,
        o if o == Instructionsx86::JLE1 as u32=>return true,
        o if o == Instructionsx86::JLE2 as u32=>return true,
        o if o == Instructionsx86::JLE4 as u32=>return true,
        o if o == Instructionsx86::JL1 as u32=>return true,
        o if o == Instructionsx86::JL2 as u32=>return true,
        o if o == Instructionsx86::JL4 as u32=>return true,
        o if o == Instructionsx86::JMP16m as u32=>return true,
        o if o == Instructionsx86::JMP16r as u32=>return true,
        o if o == Instructionsx86::JMP32m as u32=>return true,
        o if o == Instructionsx86::JMP32r as u32=>return true,
        o if o == Instructionsx86::JMP64m as u32=>return true,
        o if o == Instructionsx86::JMP64r as u32=>return true,
        o if o == Instructionsx86::JMP1 as u32=>return true,
        o if o == Instructionsx86::JMP2 as u32=>return true,
        o if o == Instructionsx86::JMP4 as u32=>return true,
        o if o == Instructionsx86::JNE1 as u32=>return true,
        o if o == Instructionsx86::JNE2 as u32=>return true,
        o if o == Instructionsx86::JNE4 as u32=>return true,
        o if o == Instructionsx86::JNO1 as u32=>return true,
        o if o == Instructionsx86::JNO2 as u32=>return true,
        o if o == Instructionsx86::JNO4 as u32=>return true,
        o if o == Instructionsx86::JNP1 as u32=>return true,
        o if o == Instructionsx86::JNP2 as u32=>return true,
        o if o == Instructionsx86::JNP4 as u32=>return true,
        o if o == Instructionsx86::JNS1 as u32=>return true,
        o if o == Instructionsx86::JNS2 as u32=>return true,
        o if o == Instructionsx86::JNS4 as u32=>return true,
        o if o == Instructionsx86::JO1 as u32=>return true,
        o if o == Instructionsx86::JO2 as u32=>return true,
        o if o == Instructionsx86::JO4 as u32=>return true,
        o if o == Instructionsx86::JP1 as u32=>return true,
        o if o == Instructionsx86::JP2 as u32=>return true,
        o if o == Instructionsx86::JP4 as u32=>return true,
        o if o == Instructionsx86::JRCXZ as u32=>return true,
        o if o == Instructionsx86::JS1 as u32=>return true,
        o if o == Instructionsx86::JS2 as u32=>return true,
        o if o == Instructionsx86::JS4 as u32=>return true,
        o if o == Instructionsx86::CALL16m as u32=>return true,
        o if o == Instructionsx86::CALL16r as u32=>return true,
        o if o == Instructionsx86::CALL32m as u32=>return true,
        o if o == Instructionsx86::CALL32r as u32=>return true,
        o if o == Instructionsx86::CALL64m as u32=>return true,
        o if o == Instructionsx86::CALL64pcrel32 as u32=>return true,
        o if o == Instructionsx86::CALL64r as u32=>return true,
        o if o == Instructionsx86::CALLpcrel16 as u32=>return true,
        o if o == Instructionsx86::CALLpcrel32 as u32=>return true,
        o if o == Instructionsx86::RETIL as u32=>return true,
        o if o == Instructionsx86::RETIQ as u32=>return true,
        o if o == Instructionsx86::RETIW as u32=>return true,
        o if o == Instructionsx86::RETL as u32=>return true,
        o if o == Instructionsx86::RETQ as u32=>return true,
        o if o == Instructionsx86::RETW as u32=>return true,
        o if o == Instructionsx86::LRETIL as u32=>return true,
        o if o == Instructionsx86::LRETIQ as u32=>return true,
        o if o == Instructionsx86::LRETIW as u32=>return true,
        o if o == Instructionsx86::LRETL as u32=>return true,
        o if o == Instructionsx86::LRETQ as u32=>return true,
        o if o == Instructionsx86::LRETW as u32=>return true,
        _=>return false,
    }
}

fn check_rep(_opcode: &u32) -> bool{
    match *_opcode {
        o if o == Instructionsx86::MOVSB as u32=>return true,
        o if o == Instructionsx86::MOVSL as u32=>return true,
        o if o == Instructionsx86::MOVSQ as u32=>return true,
        o if o == Instructionsx86::MOVSW as u32=>return true,
        o if o == Instructionsx86::OUTSB as u32=>return true,
        o if o == Instructionsx86::OUTSL as u32=>return true,
        o if o == Instructionsx86::OUTSW as u32=>return true,
        o if o == Instructionsx86::STOSB as u32=>return true,
        o if o == Instructionsx86::STOSL as u32=>return true,
        o if o == Instructionsx86::STOSQ as u32=>return true,
        o if o == Instructionsx86::STOSW as u32=>return true,
        o if o == Instructionsx86::INSB as u32=>return true,
        o if o == Instructionsx86::INSL as u32=>return true,
        o if o == Instructionsx86::INSW as u32=>return true,
        o if o == Instructionsx86::LODSB as u32=>return true,
        o if o == Instructionsx86::LODSL as u32=>return true,
        o if o == Instructionsx86::LODSQ as u32=>return true,
        o if o == Instructionsx86::LODSW as u32=>return true,
        o if o == Instructionsx86::MOVSL as u32=>return true,
        o if o == Instructionsx86::LODSL as u32=>return true,
        o if o == Instructionsx86::STOSL as u32=>return true,
        _=>return false,
    }
}

fn check_repz(_opcode: &u32) -> bool{
    match *_opcode {
        o if o == Instructionsx86::CMPSB as u32=>return true,
        o if o == Instructionsx86::CMPSQ as u32=>return true,
        o if o == Instructionsx86::CMPSW as u32=>return true,
        o if o == Instructionsx86::SCASB as u32=>return true,
        o if o == Instructionsx86::SCASQ as u32=>return true,
        o if o == Instructionsx86::SCASW as u32=>return true,
        o if o == Instructionsx86::CMPSL as u32=>return true,
        o if o == Instructionsx86::SCASL as u32=>return true,
        _=>return false,
    }
}

fn check_repnz(_opcode: &u32) -> bool{
    match *_opcode {
        o if o == Instructionsx86::CMPSB as u32=>return true,
        o if o == Instructionsx86::CMPSQ as u32=>return true,
        o if o == Instructionsx86::CMPSW as u32=>return true,
        o if o == Instructionsx86::SCASB as u32=>return true,
        o if o == Instructionsx86::SCASQ as u32=>return true,
        o if o == Instructionsx86::SCASW as u32=>return true,
        o if o == Instructionsx86::CMPSL as u32=>return true,
        o if o == Instructionsx86::SCASL as u32=>return true,
        o if o == Instructionsx86::MOVSB as u32=>return true,
        o if o == Instructionsx86::MOVSDmr as u32=>return true,
        o if o == Instructionsx86::MOVSDrm as u32=>return true,
        o if o == Instructionsx86::MOVSDrr as u32=>return true,
        o if o == Instructionsx86::MOVSDrrREV as u32=>return true,
        o if o == Instructionsx86::MOVSL as u32=>return true,
        o if o == Instructionsx86::MOVSQ as u32=>return true,
        o if o == Instructionsx86::MOVSW as u32=>return true,
        o if o == Instructionsx86::LODSB as u32=>return true,
        o if o == Instructionsx86::LODSL as u32=>return true,
        o if o == Instructionsx86::LODSQ as u32=>return true,
        o if o == Instructionsx86::LODSW as u32=>return true,
        o if o == Instructionsx86::INSB as u32=>return true,
        o if o == Instructionsx86::INSL as u32=>return true,
        o if o == Instructionsx86::INSW as u32=>return true,
        o if o == Instructionsx86::OUTSB as u32=>return true,
        o if o == Instructionsx86::OUTSL as u32=>return true,
        o if o == Instructionsx86::OUTSW as u32=>return true,
        o if o == Instructionsx86::STOSB as u32=>return true,
        o if o == Instructionsx86::STOSL as u32=>return true,
        o if o == Instructionsx86::STOSQ as u32=>return true,
        o if o == Instructionsx86::STOSW as u32=>return true,
        _=>return false,
    }
}

fn print_prefix(
    _nmemonic: &mut String,
    _prefix: &u8,
    _opcode: &u32)
{
    disasm_debug!("print_prefix()");
    match *_prefix{
        0xF0 =>{ /* Lock */
            *_nmemonic = format!("lock {}", *_nmemonic);
        },
        0xF2 =>{ /* REPNE/REPNZ */
            if check_repnz(_opcode){
                *_nmemonic = format!("repnz {}", *_nmemonic);
            } else if check_bnd(_opcode){
                *_nmemonic = format!("bnd {}", *_nmemonic);
            }
        },
        0xF3 =>{ /* REP or REPE/REPZ */
            if check_rep(_opcode){
                *_nmemonic = format!("rep {}", *_nmemonic);
            } else if check_repz(_opcode){
                *_nmemonic = format!("repz {}", *_nmemonic);
            }
        },
        _=>{},
    }
}

pub fn build_instruction<T: ArchDetail + Debug>(
    _instr_int: &Instructionx86,
    _instr_ext: &mut Instruction<T>,
    ) -> bool
{
    disasm_debug!("build_instruction()");
    if _instr_int.instr_spec.is_none() {
        disasm_debug!("_instr_int.instr_spec is 0");
        return false;
    }

    // Set Opcode
    _instr_ext.opcode = _instr_int.instr_index as u32;
    // print mnemonic
    let opcode = print_opcode(_instr_ext.opcode as usize);
    _instr_ext.mnemonic.push_str(opcode);
    // address
    _instr_ext.address = _instr_int.start;
    // size
    _instr_ext.size = _instr_int.length;

    // detail:
    // prefix
    let mut prefix = _instr_int.prefix.location;
    prefix.sort();
    let mut count = 0;
    for i in ::num::iter::range(0, prefix.len()){
        if prefix[i] > 0{
            let _prefix = _instr_int.cinfo.code[(prefix[i]-_instr_int.cinfo.address) as usize];
            _instr_ext.detail.prefix()[count] = _prefix;
            print_prefix(
                &mut _instr_ext.mnemonic,
                &_prefix,
                &_instr_ext.opcode);
            count+=1;
        }
    }
    // opcode
    if _instr_int.prefix.vex_type != VexExType::NoXop{
        *_instr_ext.detail.opcode() = _instr_int.prefix.vex_prefix;
    }
    else {
        if _instr_int.opcode.escape_byte2 != 0{
            if _instr_int.opcode.escape_byte3 != 0 {
                _instr_ext.detail.opcode()[0] = _instr_int.opcode.escape_byte2;
                _instr_ext.detail.opcode()[1] = _instr_int.opcode.escape_byte3;
                _instr_ext.detail.opcode()[2] = _instr_int.opcode.data[(_instr_int.opcode.size-1) as usize];

            } else {
                _instr_ext.detail.opcode()[0] = _instr_int.opcode.escape_byte2;
                _instr_ext.detail.opcode()[1] = _instr_int.opcode.data[(_instr_int.opcode.size-1) as usize];
            }

        } else {
            *_instr_ext.detail.opcode() = _instr_int.opcode.data;
        }
    }
    // rex
    *_instr_ext.detail.rex() = _instr_int.prefix.kind[PrefixMaskx86::Rex as usize];
    // address_size
    *_instr_ext.detail.address_size() = _instr_int.size.address;
    // mod_rm
    match _instr_int.mod_rm{
        Some(ref rm)=>{
            *_instr_ext.detail.mod_rm() = rm.data as u8;
            match rm.sib{
                Some(ref s)=>{
                    *_instr_ext.detail.sib() = s.data;
                    *_instr_ext.detail.sib_index() = s.sib_index as u16;
                    *_instr_ext.detail.sib_scale() = s.sib_scale;
                    *_instr_ext.detail.sib_base() = s.sib_base as u16;
                },
                None=>{},
            }
            match rm.displacement{
                Some(ref disp)=>{
                    *_instr_ext.detail.displacement() = disp.data;
                },
                None=>{},
            }
        }
        None=>{},
    }
    // handle xAcquireRelease
    if _instr_int.prefix.x_acquire_release {
        if _instr_ext.opcode == Instructionsx86::REPPREFIX as u32{
            _instr_ext.opcode = Instructionsx86::XRELEASEPREFIX as u32;
        }
        else if _instr_ext.opcode == Instructionsx86::REPNEPREFIX as u32{
            _instr_ext.opcode = Instructionsx86::XACQUIREPREFIX as u32;
        }
    }

    // TODO: AVX Special Cases

    // first operand
    let first_operand = DISASMX86_FIRST_OP_MAP[_instr_ext.opcode as usize];
    if first_operand != 0 {
        disasm_debug!("adding first operand");
        build_register(
            &mut _instr_ext.detail, 
            &mut _instr_ext.op_str,
            first_operand,
            _instr_int.operand_size as u8);
        match _instr_int.operands
        {
            Some(ref operands)=>{
                if operands[0].encoding != OperandEncodingx86::ENCODINGNONE
                { 
                    _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
                }
            }
            None=>{},
        }
    }
    // operands
    let mut immediates_translated: usize = 0;
    if _instr_int.operands.is_some(){
        let mut index: usize = 0;
        while index < 6 {
            match _instr_int.operands
            {
                Some(ref operands)=>{
                    if !build_operand(
                        _instr_int,
                        &operands[index], 
                        &mut index,
                        _instr_ext,
                        &mut immediates_translated)
                    {
                        return false;
                    }
                },
                None=>{},
            }
            index+=1;
        }
    }
    // check printing opcode
    if *_instr_ext.detail.printing_opcode() != 0 {
        let opcode = print_opcode(*_instr_ext.detail.printing_opcode() as usize);
        _instr_ext.mnemonic.clear();
        _instr_ext.mnemonic.push_str(opcode);
    }

    // last operand
    let last_operand = DISASMX86_LAST_OP_MAP[_instr_ext.opcode as usize];

    if last_operand != 0 && first_operand == 0 {
        _instr_ext.op_str= format!("{}, ", _instr_ext.op_str);
        disasm_debug!("adding last operand");
        build_register(
            &mut _instr_ext.detail, 
            &mut _instr_ext.op_str,
            last_operand,
            _instr_int.operand_size as u8);
        
    }

    // bytes
    let mut cursor = (_instr_int.cinfo.offset - _instr_int.cinfo.address) as usize;
    let mut index = 0;
    let mut size = cursor + _instr_int.length as usize;
    if size > _instr_int.cinfo.size{
        size = _instr_int.cinfo.size;
    }
    while cursor < size && index < _instr_ext.bytes.len(){
        _instr_ext.bytes[index] = _instr_int.cinfo.code[cursor];
        index+=1;
        cursor+=1;
    }
    return true;
}